Datasheet AD7762 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 625 kSPS, 24-Bit, 109 dB Sigma-Delta ADC with On-Chip Buffer |
| Pages / Page | 29 / 6 — Data Sheet. AD7762. TIMING SPECIFICATIONS. Table 3. Parameter. Limit at … |
| Revision | A |
| File Format / Size | PDF / 628 Kb |
| Document Language | English |
Data Sheet. AD7762. TIMING SPECIFICATIONS. Table 3. Parameter. Limit at TMIN, TMAX. Unit. Description. TIMING DIAGRAMS. DRDY. RD/WR
Model Line for this Datasheet
Text Version of Document
link to page 6 link to page 6
Data Sheet AD7762 TIMING SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
fMCLK 1 MHz min Applied master clock frequency 40 MHz max fICLK 500 kHz min Internal modulator clock derived from MCLK 20 MHz max t 1, 2 1 0.5 × tICLK typ DRDY pulse width t2 10 ns min DRDY falling edge to CS falling edge t3 3 ns min RD/WR setup time to CS falling edge t4 (0.5 × tICLK) + 16 ns max Data access time t5 tICLK min CS low read pulse width t6 tICLK min CS high pulse width between reads t7 3 ns min RD/WR hold time to CS rising edge t8 11 ns max Bus relinquish time t9 4 × tICLK min CS low write pulse width t10 4 × tICLK min CS high period between address and data t11 5 ns min Data setup time t12 0 ns min Data hold time 1 tICLK = 1/fICLK. 2 When ICLK = MCLK, DRDY pulse width depends on the mark/space ratio of applied MCLK.
TIMING DIAGRAMS DRDY t t 1 5 t6 CS t2 t t 7 3 RD/WR t t 4 8 D[0:15] DATA MSW LSW + STATUS
05477-002 Figure 2. Parallel Interface Timing Diagram
CS t9 t10 RD/WR t11 t12 D[0:15] REGISTER ADDRESS REGISTER DATA
05477-004 Figure 3. AD7762 Register Write Rev. A | Page 5 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation AD7762 Interface Reading Data Sharing the Parallel Bus Writing to the AD7762 Reading Status and Other Registers Clocking the AD7762 Example 1 Example 2 Driving the AD7762 Using the AD7762 Bias Resistor Selection Decoupling and Layout Recommendations Supply Decoupling Additional Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Programmable FIR Filter Downloading a User-Defined Filter Example Filter Download AD7762 Registers Control Register 1—Reg 0x0001 Default Value 0x001A Control Register 2—Address 0x0002 Default Value 0x009B Status Register (Read Only) Offset Register—Address 0x0003 Non-bitmapped, Default Value 0x0000 Gain Register—Address 0x0004 Non-bitmapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-bitmapped, Default Value 0xCCCC Outline Dimensions Ordering Guide
Data Sheet AD7762 TIMING SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
fMCLK 1 MHz min Applied master clock frequency 40 MHz max fICLK 500 kHz min Internal modulator clock derived from MCLK 20 MHz max t 1, 2 1 0.5 × tICLK typ DRDY pulse width t2 10 ns min DRDY falling edge to CS falling edge t3 3 ns min RD/WR setup time to CS falling edge t4 (0.5 × tICLK) + 16 ns max Data access time t5 tICLK min CS low read pulse width t6 tICLK min CS high pulse width between reads t7 3 ns min RD/WR hold time to CS rising edge t8 11 ns max Bus relinquish time t9 4 × tICLK min CS low write pulse width t10 4 × tICLK min CS high period between address and data t11 5 ns min Data setup time t12 0 ns min Data hold time 1 tICLK = 1/fICLK. 2 When ICLK = MCLK, DRDY pulse width depends on the mark/space ratio of applied MCLK.
TIMING DIAGRAMS DRDY t t 1 5 t6 CS t2 t t 7 3 RD/WR t t 4 8 D[0:15] DATA MSW LSW + STATUS
05477-002 Figure 2. Parallel Interface Timing Diagram
CS t9 t10 RD/WR t11 t12 D[0:15] REGISTER ADDRESS REGISTER DATA
05477-004 Figure 3. AD7762 Register Write Rev. A | Page 5 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation AD7762 Interface Reading Data Sharing the Parallel Bus Writing to the AD7762 Reading Status and Other Registers Clocking the AD7762 Example 1 Example 2 Driving the AD7762 Using the AD7762 Bias Resistor Selection Decoupling and Layout Recommendations Supply Decoupling Additional Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Programmable FIR Filter Downloading a User-Defined Filter Example Filter Download AD7762 Registers Control Register 1—Reg 0x0001 Default Value 0x001A Control Register 2—Address 0x0002 Default Value 0x009B Status Register (Read Only) Offset Register—Address 0x0003 Non-bitmapped, Default Value 0x0000 Gain Register—Address 0x0004 Non-bitmapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-bitmapped, Default Value 0xCCCC Outline Dimensions Ordering Guide
