Datasheet AD7276, AD7277, AD7278 (Analog Devices) - 8

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AD7276/AD7277/AD7278 Data Sheet Parameter A Grade1, 2 B Grade1, 2 Unit Test Conditions/Comments
POWER REQUIREMENTS V 2.35/3.6 2.35/3.6 V min/max DD I Digital I/Ps = 0 V or V DD DD Normal Mode (Static) 0.5 0.5 mA typ V = 3.6 V, SCLK on or off DD Normal Mode (Operational) 5.5 5.5 mA max V = 2.35 V to 3.6 V, f = 3 MSPS DD SAMPLE 3.5 3.5 mA typ V = 3 V DD Partial Power-Down Mode (Static) 34 34 µA typ Full Power-Down Mode (Static) 2 2 µA max −40°C to +85°C, typically 0.1 µA 10 10 µA max +85°C to +125°C Power Dissipation5 Normal Mode (Operational) 19.8 19.8 mW max V = 3.6 V, f = 3 MSPS DD SAMPLE 10.5 10.5 mW typ V = 3 V DD Partial Power-Down 102 102 µW typ V = 3 V DD Full Power-Down 7.2 7.2 µW max V = 3.6 V, −40°C to +85°C DD 1 Temperature range from −40°C to +125°C. 2 Typical specifications are tested with VDD = 3 V and at 25°C. 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section.
TIMING SPECIFICATIONS—AD7276/ AD7277/ AD7278
VDD = 2.35 V to 3.6 V, TA = TMIN to TMAX, unless otherwise noted.1
Table 5. Parameter2 Limit at T , T Unit Description MIN MAX
f 3 500 kHz min4 SCLK 48 MHz max B grade 16 MHz max Y grade t 14 × t AD7276 CONVERT SCLK 12 × t AD7277 SCLK 10 × t AD7278 SCLK t 4 ns min Minimum quiet time required between the bus relinquish and the QUIET start of the next conversion t 3 ns min Minimum 1 CS pulse width t 6 ns min 2 CS to SCLK setup time t 5 4 ns max Delay from 3 CS until SDATA three-state disabled t 5 15 ns max Data access time after SCLK falling edge 4 t 0.4 t ns min SCLK low pulse width 5 SCLK t 0.4 t ns min SCLK high pulse width 6 SCLK t 5 5 ns min SCLK to data valid hold time 7 t 14 ns max SCLK falling edge to SDATA three-state 8 5 ns min SCLK falling edge to SDATA three-state t 4.2 ns max 9 CS rising edge to SDATA three-state T 6 1 µs max Power-up time from full power-down POWER-UP 1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. 2 Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 3 Mark/space ratio for the SCLK input is 40/60 to 60/40. 4 Minimum fSCLK at which specifications are guaranteed. 5 The time required for the output to cross the VIH or VIL voltage. 6 See the Power-Up Times section. Rev. D | Page 8 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7276 SPECIFICATIONS AD7277 SPECIFICATIONS AD7278 SPECIFICATIONS TIMING SPECIFICATIONS—AD7276/AD7277/AD7278 TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM Analog Input Digital Inputs MODES OF OPERATION Normal Mode Partial Power-Down Mode Full Power-Down Mode Power-Up Times POWER VS. THROUGHPUT RATE SERIAL INTERFACE AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7276/AD7277/AD7278 to Blackfin Processor APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE NOTES