Datasheet AD7276, AD7277, AD7278 (Analog Devices) - 10

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AD7276/AD7277/AD7278 Data Sheet TIMING EXAMPLES
This satisfies the requirement of 60 ns for tACQ. Figure 6 also For the AD7276, if shows that t CS is brought high during the 14th SCLK rising ACQ comprises 0.5(1/fSCLK) + t8 + tQUIET, where t edge after the two leading zeros and 12 bits of the conversion 8 = 14 ns max. This allows a value of 43 ns for tQUIET, satisfying the minimum requirement of 4 ns. have been provided, the part can achieve the fastest throughput rate, 3 MSPS. If CS is brought high during the 16th SCLK rising
Timing Example 2
edge after the two leading zeros and 12 bits of the conversion The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz, and two trailing zeros have been provided, a throughput rate of and the throughput is 2.97 MSPS. This produces a cycle time of 2.97 MSPS is achievable. This is illustrated in the following two t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns minimum and timing examples. tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) + t8 +
Timing Example 1
tQUIET, where t8 = 14 ns max. This satisfies the minimum requirement of 4 ns for tQUIET. In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz and the throughput is 3 MSPS. This produces a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns minimum and tACQ = 67 ns.
t1 CS tCONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t5 t t 8 3 t t 7 t 4 QUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 ZERO ZERO THREE- THREE-STATE STATE 2 LEADING 2 TRAILING
05
ZEROS ZEROS
0 3-
1/THROUGHPUT
490 0 Figure 5. AD7276 Serial Interface Timing Diagram
t1 CS tCONVERT t2 t B 6 SCLK 1 2 3 4 5 13 14 t7 t t 5 t 9 3 tQUIET t4 SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 THREE- THREE-STATE STATE 2 LEADING
4
ZEROS
-03 3
1/THROUGHPUT
90 04 Figure 6. AD7276 Serial Interface Timing 14 SCLK Cycle
t1 CS tCONVERT t2 B SCLK 1 2 3 4 5 12 13 14 15 16 t8 tQUIET 12.5(1/f
6
SCLK) tACQUISITION
-00
1/THROUGHPUT
903 04 Figure 7. AD7276 Serial Interface Timing 16 SCLK Cycle Rev. D | Page 10 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7276 SPECIFICATIONS AD7277 SPECIFICATIONS AD7278 SPECIFICATIONS TIMING SPECIFICATIONS—AD7276/AD7277/AD7278 TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM Analog Input Digital Inputs MODES OF OPERATION Normal Mode Partial Power-Down Mode Full Power-Down Mode Power-Up Times POWER VS. THROUGHPUT RATE SERIAL INTERFACE AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7276/AD7277/AD7278 to Blackfin Processor APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE NOTES