Datasheet AD7266 (Analog Devices)

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Differential/Single-Ended Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC AD7266 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual 12-bit, 3-channel ADC REF SELECT DCAPA AVDD DVDD Throughput rate: 2 MSPS Specified for V REF BUF DD of 2.7 V to 5.25 V AD7266 Power consumption V 9 mW at 1.5 MSPS with 3 V supplies A1 VA2 27 mW at 2 MSPS with 5 V supplies 12-BIT VA3 SUCCESSIVE OUTPUT Pin-configurable analog inputs MUX T/H APPROXIMATION DOUTA DRIVERS VA4 ADC 12-channel single-ended inputs VA5 6-channel fully differential inputs SCLK VA6 CS 6-channel pseudo differential inputs RANGE 70 dB SNR at 50 kHz input frequency CONTROL SGL/DIFF LOGIC A0 Accurate on-chip reference: 2.5 V A1 ±0.2% maximum @ 25°C, 20 ppm/°C maximum V A2 B1 Dual conversion with read 437.5 ns, 32 MHz SCLK VB2 VDRIVE High speed serial interface VB3 MUX 12-BIT SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible VB4 SUCCESSIVE OUTPUT D T/H OUTB APPROXIMATION DRIVERS −40°C to +125°C operation V ADC B5 Shutdown mode: 1 μA maximum VB6 32-lead LFCSP and 32-lead TQFP BUF 1 MSPS version, AD7265 GENERAL DESCRIPTION AGND AGND AGND DCAPB DGND DGND
04603-001 The AD72661 is a dual, 12-bit, high speed, low power, successive Figure 1. approximation ADC that operates from a single 2.7 V to 5.25 V The AD7266 is available in a 32-lead LFCSP and a power supply and features throughput rates up to 2 MSPS. The 32-lead TQFP. device contains two ADCs, each preceded by a 3-channel
PRODUCT HIGHLIGHTS
multiplexer, and a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 30 MHz. 1. Two Complete ADC Functions Allow Simultaneous Sampling and Conversion of Two Channels. The conversion process and data acquisition use standard Each ADC has three fully/pseudo differential pairs, or six control inputs allowing easy interfacing to microprocessors or single-ended channels, as programmed. The conversion DSPs. The input signal is sampled on the falling edge of CS; result of both channels is simultaneously available on conversion is also initiated at this point. The conversion time is separate data lines, or in succession on one data line if only determined by the SCLK frequency. There are no pipelined one serial port is available. delays associated with the part. 2. High Throughput with Low Power Consumption. The AD7266 uses advanced design techniques to achieve very The AD7266 offers a 1.5 MSPS throughput rate with 11.4 mW low power dissipation at high throughput rates. With 5 V maximum power dissipation when operating at 3 V. supplies and a 2 MSPS throughput rate, the part consumes 3. The AD7266 offers both a standard 0 V to VREF input range 6.2 mA maximum. The part also offers flexible power/ and a 2 × VREF input range. throughput rate management when operating in normal mode 4. No Pipeline Delay. as the quiescent current consumption is so low. The part features two standard successive approximation The analog input range for the part can be selected to be a 0 V ADCs with accurate control of the sampling instant via a to VREF (or 2 × VREF) range, with either straight binary or twos CS input and once off conversion control. complement output coding. The AD7266 has an on-chip 2.5 V reference that can be overdriven when an external reference is 1 Protected by U.S. Patent No. 6,681,332 preferred. This external reference range is 100 mV to VDD.
Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2005–2011 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT STRUCTURE ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode ANALOG INPUT SELECTION OUTPUT CODING TRANSFER FUNCTIONS DIGITAL INPUTS VDRIVE MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER vs. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7266 TO ADSP-218x AD7266 TO ADSP-BF53x AD7266 TO TMS320C541 AD7266 TO DSP563xx APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP EVALUATING THE AD7266 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE