Datasheet AD9289 (Analog Devices) - 8

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AD9289 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 A B C D E F G H
03682-005 Figure 3. BGA Top View (Looking Through)
Table 6. Pin Function Descriptions Pin Pin No. Mnemonic Description No. Mnemonic Description
A1 D1–A ADC A Complement Digital Output D5 AGND Analog Ground B1 D1+A ADC A True Digital Output E5 AGND Analog Ground C1 FCO+ Frame Clock Output (MSB Indicator) F5 REFT_B Reference Buffer Decoupling (Positive) True Output G5 REFB_B Reference Buffer Decoupling (Negative) D1 DNC Do Not Connect H5 VREF Voltage Reference Input/Output E1 AGND Analog Ground A6 DNC Do Not Connect F1 VIN–A ADC A Analog Input—Complement B6 DNC Do Not Connect G1 VIN+A ADC A Analog Input—True C6 DRVDD Digital Supply H1 LVDSBIAS1 LVDS Output Bias Pin D6 DRGND Digital Ground A2 DNC Do Not Connect E6 AVDD Analog Supply B2 DNC Do Not Connect F6 AGND Analog Ground C2 FCO– Frame Clock Output (MSB Indicator) G6 AGND Analog Ground Complement Output H6 VIN–C ADC C Analog Input—Complement D2 DNC Do Not Connect A7 D1–D ADC D Complement Digital Output E2 AGND Analog Ground B7 D1+D ADC D True Digital Output F2 AVDD Analog Supply C7 DFS2 Data Format Select G2 AGND Analog Ground D7 AGND Analog Ground H2 VIN+B ADC B Analog Input—True E7 AGND Analog Ground A3 D1–B ADC B Complement Digital Output F7 AVDD Analog Supply B3 D1+B ADC B True Digital Output G7 AGND Analog Ground C3 DRVDD Digital Supply H7 VIN+C ADC C Analog Input—True D3 DRGND Digital Ground A8 DNC Do Not Connect E3 AGND Analog Ground B8 DNC Do Not Connect F3 CML Common Mode Level Output ( = AVDD/2) C8 CLK+ Input Clock—True G3 SHARED_REF3 Shared Reference Control Bit D8 CLK– Input Clock—Complement H3 VIN–B ADC B Analog Input—Complement E8 PDWN3 Power Down Selection A4 DNC Do Not Connect F8 VIN–D ADC D Analog Input—Complement B4 DNC Do Not Connect G8 VIN+D ADC D Analog Input—True C4 DCO+ Data Clock Output—True H8 DTP3, 4 Digital Test Pattern D4 LOCK PLL Lock Output E4 AVDD Analog Supply F4 REFT_A Reference Buffer Decoupling (Positive) 1 LVDSBIAS use a 3.9 kΩ resistor-to-analog ground to set the LVDS output differential swing of 350 mV p-p. G4 REFB_A Reference Buffer Decoupling (Negative) 2 DFS has an internal on-chip pull-down resistor and defaults to offset binary H4 SENSE Reference Mode Selection output coding if untied. If twos complement output coding is desired then A5 D1–C ADC C Complement Digital Output tie this pin to AVDD. 3 To enable, tie this pin to AVDD. To disable, tie this pin to AGND. B5 D1+C ADC C True Digital Output 4 DTP has an internal on-chip pull-down resistor. C5 DCO– Data Clock Output—Complement Rev. 0 | Page 7 of 32 Document Outline FEATURES PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS Power Dissipation and Standby Mode Digital Outputs Timing Pin CML Pin DTP Pin Voltage Reference Internal Reference Connection External Reference Operation Power and Ground Recommendations EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE