Datasheet AD7457 (Analog Devices)

Low Power, Pseudo Differential, 100 kSPS 12-Bit ADC in an 8-Lead SOT-23 AD7457 FEATURES FUNCTIONAL BLOCK DIAGRAM Specified for VDD of 2.7 V to 5.25 V VDD Low power: 0.9 mW max at 100 kSPS with VDD = 3 V 3 mW max at 100 kSPS with VDD = 5 V Pseudo differential analog input VIN+ 12-BIT Wide input bandwidth: T/H SUCCESSIVE APPROXIMATION V 70 dB SINAD at 30 kHz input frequency IN– ADC Flexible power/serial clock speed management VREF No pipeline delays High speed serial interface—SPI®-/QSPI™-/ MICROWIRE™-/DSP-compatible SCLK Automatic power-down mode SDATA AD7457 CONTROL LOGIC 8-lead SOT-23 package CS APPLICATIONS Transducer interface GND 03157-0-013 Battery-powered systems Data acquisition systems
Figure 1.
Portable instrumentation GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD7457 is a 12-bit, low power, successive approximation 1. Operation with 2.7 V to 5.25 V power supplies. (SAR) analog-to-digital converter that features a pseudo 2. Low power consumption. With a 3 V supply, the AD7457 differential analog input. This part operates from a single 2.7 V offers 0.9 mW maximum power consumption for a to 5.25 V power supply and features throughput rates of up to 100 kSPS throughput rate. 100 kSPS. 3. Pseudo differential analog input. 4. Flexible power/serial clock speed management. The The part contains a low noise, wide bandwidth, differential conversion rate is determined by the serial clock, allowing track-and-hold (T/H) amplifier that can handle input frequen- the power to be reduced as the conversion time is reduced cies in excess of 1 MHz. The reference voltage for the AD7457 is through the serial clock speed increase. Automatic power- applied externally to the VREF pin and can range from 100 mV to down after conversion allows the average power consump- VDD, depending on what suits the application. tion to be reduced. 5. Variable voltage reference input. The conversion process and data acquisition are controlled 6. No pipeline delays. using CS and the serial clock, allowing the device to interface 7. Accurate control of the sampling instant via the CS input with microprocessors or DSPs. The SAR architecture of this and once-off conversion control. part ensures that there are no pipeline delays. 8. ENOB > 10 bits typically with 500 mV reference. The AD7457 uses advanced design techniques to achieve very low power dissipation.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT ANALOG INPUT STRUCTURE DIGITAL INPUTS REFERENCE SECTION SERIAL INTERFACE POWER CONSUMPTION MICROPROCESSOR INTERFACING AD7457 to ADSP-218x APPLICATION HINTS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE