link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 14 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 AD7457SPECIFICATIONS VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 100 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted. Table 1. ParameterTest Conditions/CommentsB Version1Unit DYNAMIC PERFORMANCE fIN = 30 kHz Signal to Noise Ratio (SNR)2 71 dB min Signal to (Noise + Distortion) (SINAD)2 70 dB min Total Harmonic Distortion (THD)2 −84 dB typ −75 dB max Peak Harmonic or Spurious Noise2 −86 dB typ −75 dB max Intermodulation Distortion (IMD)2 fa = 25 kHz; fb = 35 kHz Second-Order Terms −80 dB typ Third-Order Terms −80 dB typ Aperture Delay2 5 ns typ Aperture Jitter2 50 ps typ Full-Power Bandwidth2, 3 @ −3 dB 20 MHz typ @ −0.1 dB 2.5 MHz typ DC ACCURACY Resolution 12 Bits Integral Nonlinearity (INL)2 ±1 LSB max Differential Nonlinearity (DNL)2 Guaranteed no missed codes to 12 bits ±0.95 LSB max Offset Error2 ±4.5 LSB max Gain Error2 ±2 LSB max ANALOG INPUT Full-Scale Input Span VIN+ − VIN− VREF V Absolute Input Voltage VIN+ VREF V V 4 IN− VDD = 2.7 V to 3.6 V −0.1 to +0.4 V VDD = 4.75 V to 5.25 V −0.1 to +1.5 V DC Leakage Current ±1 µA max Input Capacitance When in track/hold 30/10 pF typ REFERENCE INPUT VREF Input Voltage5 ±1% tolerance for specified performance 2.5 V DC Leakage Current ±1 µA max VREF Input Capacitance When in track/hold 10/30 pF typ LOGIC INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 µA max Input Capacitance, C 6 IN 10 pF max LOGIC OUTPUTS Output High Voltage, VOH VDD = 4.75 V to 5.25 V, ISOURCE = 200 µA 2.8 V min VDD = 2.7 V to 3.6 V, ISOURCE = 200 µA 2.4 V min Output Low Voltage, VOL ISINK = 200 µA 0.4 V max Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance6 10 pF max Output Coding Straight natural binary CONVERSION RATE Conversion Time 1.6 µs with a 10 MHz SCLK 16 SCLK cycles Track-and-Hold Acquisition Time2 1 µs max Throughput Rate See the Serial Interface section 100 kSPS max Rev. A | Page 3 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT ANALOG INPUT STRUCTURE DIGITAL INPUTS REFERENCE SECTION SERIAL INTERFACE POWER CONSUMPTION MICROPROCESSOR INTERFACING AD7457 to ADSP-218x APPLICATION HINTS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE