Datasheet AD7453 (Analog Devices) - 9

AD7453 TERMINOLOGY
as per the THD specification where it is the ratio of the rms
Signal-to-(Noise + Distortion) Ratio
sum of the individual distortion products to the rms amplitude The measured ratio of signal to (noise + distortion) at the of the sum of the fundamentals expressed in dB. output of the ADC. The signal is the rms amplitude of the fun- damental. Noise is the sum of all nonfundamental signals up to
Aperture Delay
half the sampling frequency (fS/2), excluding dc. The ratio is The amount of time from the leading edge of the sampling dependent on the number of quantization levels in the digitiza- clock until the ADC actually takes the sample. tion process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by
Aperture Jitter
The sample-to-sample variation in the effective point in time at Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB which the actual sample is taken. Thus, for a 12-bit converter, this is 74 dB.
Full Power Bandwidth Total Harmonic Distortion (THD)
The full power bandwidth of an ADC is the input frequency at Total harmonic distortion is the ratio of the rms sum of which the amplitude of the reconstructed fundamental is harmonics to the fundamental. For the AD7453, it is defined as reduced by 0.1 dB or 3 dB for a full-scale input. 2 2 2 2 2 V2 + V3 + V4 + V5 + V6
Integral Nonlinearity (INL)
THD dB ( ) = 20 log V1 The maximum deviation from a straight line passing through where V the endpoints of the ADC transfer function. 1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
Peak Harmonic or Spurious Noise
change between any two adjacent codes in the ADC. Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output
Offset Error
spectrum (up to fS/2 and excluding dc) to the rms value of the The deviation of the first code transition (000...000 to 000...001) fundamental. Normally, the value of this specification is deter- from the ideal (i.e., AGND + 1 LSB) mined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise
Gain Error
peak. This is the deviation of the last code transition (111...110 to 111...111) from the ideal (i.e., VREF – 1 LSB), after the offset
Intermodulation Distortion
error has been adjusted out. With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion
Track-and-Hold Acquisition Time
products at the sum and difference frequencies of mfa ± nfb The minimum time required for the track and hold amplifier to where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion remain in track mode for its output to reach and settle to within terms are those for which neither m nor n are equal to zero. For 0.5 LSB of the applied input signal. example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at full-scale fre- The AD7453 is tested using the CCIF standard where two input quency, f, to the power of a 100 mV p-p sine wave applied to the frequencies near the top end of the input bandwidth are used. ADC VDD supply of frequency fS. The frequency of this input In this case, the second-order terms are usually distanced in varies from 1 kHz to 1 MHz. frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. PSRR(dB) = 10log(Pf/PfS) As a result, the second- and third-order terms are specified Pf is the power at frequency f in the ADC output; Pfs is the separately. The calculation of the intermodulation distortion is power at frequency fS in the ADC output. Rev. B | Page 8 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY AD7453–TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM THE ANALOG INPUT Analog Input Structure DIGITAL INPUTS REFERENCE SERIAL INTERFACE Timing Example 1 MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE MICROPROCESSOR AND DSP INTERFACING AD7453 to ADSP-21xx AD7453 to TMS320C5x/C54x AD7453 to DSP56xxx APPLICATION HINTS Grounding and Layout EVALUATING THE AD7453’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE