Datasheet AD7452 (Analog Devices) - 9

AD7452 Data Sheet TERMINOLOGY Signal-to-(Noise + Distortion) Ratio
The AD7452 is tested using the CCIF standard where two input The measured ratio of signal to (noise + distortion) at the frequencies near the top end of the input bandwidth are used. output of the ADC. The signal is the rms amplitude of the fun- In this case, the second-order terms are usually distanced in damental. Noise is the sum of all nonfundamental signals up to frequency from the original sine waves while the third-order half the sampling frequency (f terms are usual y at a frequency close to the input frequencies. S/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitiza- As a result, the second- and third-order terms are specified tion process; the more levels, the smaller the quantization noise. separately. The calculation of the intermodulation distortion is The theoretical signal-to-(noise + distortion) ratio for an ideal as per the THD specification where it is the ratio of the rms N-bit converter with a sine wave input is given by sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB. Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Aperture Delay
Thus, for a 12-bit converter, this is 74 dB. The amount of time from the leading edge of the sampling
Total Harmonic Distortion (THD)
clock until the ADC actually takes the sample. Total harmonic distortion is the ratio of the rms sum of
Aperture Jitter
harmonics to the fundamental. For the AD7452, it is defined as The sample-to-sample variation in the effective point in time at V 2 2 2 2 2 which the actual sample is taken. 2 + V 3 + V 4 + V 5 + V 6 THD ) dB ( = 20 log V1
Full Power Bandwidth
where V The ful power bandwidth of an ADC is the input frequency at 1 is the rms amplitude of the fundamental and V2, V3, V which the amplitude of the reconstructed fundamental is 4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics. reduced by 0.1 dB or 3 dB for a full-scale input.
Peak Harmonic or Spurious Noise Common-Mode Rejection Ratio (CMRR)
Peak harmonic or spurious noise is defined as the ratio of the This is the ratio of the power in the ADC output at ful -scale rms value of the next largest component in the ADC output frequency, f, to the power of a 100 mV p-p sine wave applied to spectrum (up to f the common-mode voltage of V S/2 and excluding dc) to the rms value of the IN+ and VIN– of frequency fS fundamental. Normally, the value of this specification is deter- CMRR(dB) = 10 log(Pf/Pf mined by the largest harmonic in the spectrum, but for ADCs S) where the harmonics are buried in the noise floor, it is a noise Pf is the power at the frequency f in the ADC output; PfS is the peak. power at frequency fS in the ADC output.
Intermodulation Distortion Integral Nonlinearity (INL)
With inputs consisting of sine waves at two frequencies, fa and The maximum deviation from a straight line passing through fb, any active device with nonlinearities creates distortion pro- the endpoints of the ADC transfer function. ducts at the sum and difference frequencies of mfa ± nfb where
Differential Nonlinearity (DNL)
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms The difference between the measured and the ideal 1 LSB are those for which neither m nor n are equal to zero. For change between any two adjacent codes in the ADC. example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa +
Zero Code Error
2fb) and (fa − 2fb). The deviation of the midscale code transition (111…111 to 000.. 000) from the ideal VIN+ – VIN– (that is, 0 LSB)
Positive Gain Error
This is the deviation of the last code transition (011. .110 to 011.. 111) from the ideal VIN+ – VIN– (that is, VREF – 1 LSB), after the zero code error has been adjusted out. Rev. C | Page 8 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT Analog Input Structure DRIVING DIFFERENTIAL INPUTS Differential Amplifier Op Amp Pair RF Transformer DIGITAL INPUTS REFERENCE Example 1 Example 2 SINGLE-ENDED OPERATION SERIAL INTERFACE Timing Example MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER vs. THROUGHPUT RATE APPLICATION HINTS Grounding and Layout EVALUATING THE AD7452’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE