Datasheet AD9236 (Analog Devices) - 18

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Data Sheet AD9236 TIMING
In all reference configurations, REFT and REFB drive the A/D The AD9236 provides latched data outputs with a pipeline delay conversion core and establish its input span. The input range of of seven clock cycles. Data outputs are available one propagation the ADC always equals twice the voltage at the reference pin for delay (tPD) after the rising edge of the clock signal. Refer to either an internal or an external reference. Figure 2 for a detailed timing diagram. The length of the output data lines and the loads placed on
VIN+
them should be minimized to reduce transients within the
VIN– REFT
AD9236. These transients can degrade the converter’s dynamic
0.1

F
performance.
ADC + 0.1

F 10

F CORE REFB
The lowest typical conversion rate of the AD9236 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance can degrade.
0.1

F VREF + VOLTAGE REFERENCE 10

F 0.1

F SELECT LOGIC
A stable and accurate 0.5 V voltage reference is built into the
SENSE
AD9236. The input range can be adjusted by varying the reference voltage applied to the AD9236 using either the
0.5V
internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes
AD9236
linearly. The various reference modes are summarized in Table 10 and described in the following sections. 03066-A-017 Figure 33. Internal Reference Configuration If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage).
VIN+ VIN– REFT Internal Reference Connection 0.1

F
A comparator within the AD9236 detects the potential at the
ADC + 0.1

F 10

F CORE
SENSE pin and configures the reference into four possible
REFB
states, which are summarized in Table 10. If SENSE is
0.1

F
grounded, the reference amplifier switch is connected to the
VREF
internal resistor divider (see Figure 33), setting VREF to 1 V.
+ 10

F 0.1

F SELECT
Connecting the SENSE pin to VREF switches the reference
R2 LOGIC
amplifier output to the SENSE pin, completing the loop and
SENSE
providing a 0.5 V reference output. If a resistor divider is connected as shown in Figure 34, the switch is again set to the
R1 0.5V
SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as follows:
AD9236
 R2  VREF  0.5  1   03066-0-018  R1  Figure 34. Programmable Reference Configuration
Table 10. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)
External Reference AVDD N/A 2 × External Reference Internal Fixed Reference VREF 0.5 1.0 Programmable Reference 0.2 V to VREF  R2  2 × VREF 0.5  1   (See Figure 34)  R1  Internal Fixed Reference AGND to 0.2 V 1.0 2.0 Rev. C | Page 17 of 36 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History DC Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Terminology Pin Configurations and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input and Reference Overview Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Timing Voltage Reference Internal Reference Connection External Reference Operation Operational Mode Selection Evaluation Board TSSOP Evaluation Board LFCSP Evaluation Board Outline Dimensions Ordering Guide