Datasheet AD7466, AD7467, AD7468 (Analog Devices) - 9

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AD7466/AD7467/AD7468 TIMING SPECIFICATIONS
For all devices, VDD = 1.6 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.4 V.
Table 4. Parameter Limit at TMIN, TMAX Unit Description
fSCLK 3.4 MHz max Mark/space ratio for the SCLK input is 40/60 to 60/40. 10 kHz min 1.6 V ≤ VDD ≤ 3 V; minimum fSCLK at which specifications are guaranteed. 20 kHz min VDD = 3.3 V; minimum fSCLK at which specifications are guaranteed. 150 kHz min VDD = 3.6 V; minimum fSCLK at which specifications are guaranteed. tCONVERT 16 × tSCLK AD7466. 12 × tSCLK AD7467. 10 × tSCLK AD7468. Acquisition Time Acquisition time/power-up time from power-down. See the Terminology section. The acquisition time is the time required for the part to acquire a full-scale step input value within ±1 LSB or a 30 kHz ac input value within ±0.5 LSB. 780 ns max VDD = 1.6 V. 640 ns max 1.8 V ≤ VDD ≤ 3.6 V. tQUIET 10 ns min Minimum quiet time required between bus relinquish and the start of the next conversion. t1 10 ns min Minimum CS pulse width. t2 55 ns min CS to SCLK setup time. If VDD = 1.6 V and fSCLK = 3.4 MHz, t2 has to be 192 ns minimum in order to meet the maximum figure for the acquisition time. t3 55 ns max Delay from CS until SDATA is three-state disabled. Measured with the load circuit in Figure 2 and defined as the time required for the output to cross the VIH or VIL voltage. t4 140 ns max Data access time after SCLK falling edge. Measured with the load circuit in Figure 2 and defined as the time required for the output to cross the VIH or VIL voltage. t5 0.4 tSCLK ns min SCLK low pulse width. t6 0.4 tSCLK ns min SCLK high pulse width. t7 10 ns min SCLK to data valid hold time. Measured with the load circuit in Figure 2 and defined as the time required for the output to cross the VIH or VIL voltage. t8 60 ns max SCLK falling edge to SDATA three-state. t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish time of the part, and is independent of the bus loading. 7 ns min SCLK falling edge to SDATA three-state.
200
μ
A IOL TO OUTPUT 1.4V PIN CL 50pF 200
μ
A IOH
02643-002 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. C | Page 9 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7466 AD7467 AD7468 TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DYNAMIC PERFORMANCE CURVES DC ACCURACY CURVES POWER REQUIREMENT CURVES TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS NORMAL MODE POWER CONSUMPTION Power Consumption Example 1 Power Consumption Example 2 SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7466/AD7467/AD7468 to TMS320C541 Interface AD7466/AD7467/AD7468 to ADSP-218x Interface AD7466/AD7467/AD7468 to DSP563xx Interface APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE PERFORMANCE OF THE AD7466 AND AD7467 OUTLINE DIMENSIONS ORDERING GUIDE