Datasheet AD7466, AD7467, AD7468 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 1.6 V Micro-Power 8-Bit ADC |
| Pages / Page | 28 / 10 — AD7466/AD7467/AD7468. TIMING EXAMPLES. Timing Example 2. Timing Example … |
| Revision | C |
| File Format / Size | PDF / 460 Kb |
| Document Language | English |
AD7466/AD7467/AD7468. TIMING EXAMPLES. Timing Example 2. Timing Example 1. tCONVERT. SCLK. tQUIET. ACQUISITION TIME. AUTOMATIC
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AD7466/AD7467/AD7468 TIMING EXAMPLES Timing Example 2
Figure 3 shows some of the timing parameters from Table 4 in The AD7466 can also operate with slower clock frequencies. the Timing Specifications section. As shown in Figure 3, assuming VDD = 1.8 V, fSCLK = 2 MHz, and a throughput of 50 kSPS gives a cycle time of t
Timing Example 1
CONVERT + t8 + tQUIET = 20 μs. With tCONVERT = t2 + 15(1/fSCLK) = 55 ns + 7.5 μs = As shown in Figure 3, fSCLK = 3.4 MHz and a throughput of 7.55 μs, and t8 = 60 ns maximum, this leaves tQUIET to be 12.39 100 kSPS gives a cycle time of tCONVERT + t8 + tQUIET = 10 μs. μs, which satisfies the requirement of 10 ns for tQUIET. The part is Assuming VDD = 1.8 V, tCONVERT = t2 + 15(1/fSCLK) = 55 ns + fully powered up and the signal is fully acquired at Point A, 4.41 μs = 4.46 μs, and t8 = 60 ns maximum, then tQUIET = 5.48 μs, which means the acquisition/power-up time is t2 + 2(1/fSCLK) = which satisfies the requirement of 10 ns for tQUIET. The part is 55 ns + 1 μs = 1.05 μs, satisfying the maximum requirement of fully powered up and the signal is fully acquired at Point A. 640 ns for the power-up time. In this example and with other This means that the acquisition/power-up time is t2 + 2(1/fSCLK) slower clock values, the part is fully powered up and the signal = 55 ns + 588 ns = 643 ns, satisfying the maximum requirement already acquired before the third SCLK falling edge; however, of 640 ns for the power-up time. the track-and-hold does not go into hold mode until that point. In this example, the part can be powered up and the signal can be fully acquired at approximately Point B in Figure 3.
CS tCONVERT t2 B A SCLK 1 2 3 4 5 13 14 15 16 t8 tQUIET ACQUISITION TIME AUTOMATIC POWER-DOWN TRACK-AND-HOLD IN TRACK TRACK-AND-HOLD IN HOLD 1/THROUGHPUT POINT A: THE PART IF FULLY POWERED UP WITH VIN FULLY ACQUIRED.
02643-004 Figure 3. AD7466 Serial Interface Timing Diagram Example Rev. C | Page 10 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7466 AD7467 AD7468 TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DYNAMIC PERFORMANCE CURVES DC ACCURACY CURVES POWER REQUIREMENT CURVES TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS NORMAL MODE POWER CONSUMPTION Power Consumption Example 1 Power Consumption Example 2 SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7466/AD7467/AD7468 to TMS320C541 Interface AD7466/AD7467/AD7468 to ADSP-218x Interface AD7466/AD7467/AD7468 to DSP563xx Interface APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE PERFORMANCE OF THE AD7466 AND AD7467 OUTLINE DIMENSIONS ORDERING GUIDE
AD7466/AD7467/AD7468 TIMING EXAMPLES Timing Example 2
Figure 3 shows some of the timing parameters from Table 4 in The AD7466 can also operate with slower clock frequencies. the Timing Specifications section. As shown in Figure 3, assuming VDD = 1.8 V, fSCLK = 2 MHz, and a throughput of 50 kSPS gives a cycle time of t
Timing Example 1
CONVERT + t8 + tQUIET = 20 μs. With tCONVERT = t2 + 15(1/fSCLK) = 55 ns + 7.5 μs = As shown in Figure 3, fSCLK = 3.4 MHz and a throughput of 7.55 μs, and t8 = 60 ns maximum, this leaves tQUIET to be 12.39 100 kSPS gives a cycle time of tCONVERT + t8 + tQUIET = 10 μs. μs, which satisfies the requirement of 10 ns for tQUIET. The part is Assuming VDD = 1.8 V, tCONVERT = t2 + 15(1/fSCLK) = 55 ns + fully powered up and the signal is fully acquired at Point A, 4.41 μs = 4.46 μs, and t8 = 60 ns maximum, then tQUIET = 5.48 μs, which means the acquisition/power-up time is t2 + 2(1/fSCLK) = which satisfies the requirement of 10 ns for tQUIET. The part is 55 ns + 1 μs = 1.05 μs, satisfying the maximum requirement of fully powered up and the signal is fully acquired at Point A. 640 ns for the power-up time. In this example and with other This means that the acquisition/power-up time is t2 + 2(1/fSCLK) slower clock values, the part is fully powered up and the signal = 55 ns + 588 ns = 643 ns, satisfying the maximum requirement already acquired before the third SCLK falling edge; however, of 640 ns for the power-up time. the track-and-hold does not go into hold mode until that point. In this example, the part can be powered up and the signal can be fully acquired at approximately Point B in Figure 3.
CS tCONVERT t2 B A SCLK 1 2 3 4 5 13 14 15 16 t8 tQUIET ACQUISITION TIME AUTOMATIC POWER-DOWN TRACK-AND-HOLD IN TRACK TRACK-AND-HOLD IN HOLD 1/THROUGHPUT POINT A: THE PART IF FULLY POWERED UP WITH VIN FULLY ACQUIRED.
02643-004 Figure 3. AD7466 Serial Interface Timing Diagram Example Rev. C | Page 10 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7466 AD7467 AD7468 TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DYNAMIC PERFORMANCE CURVES DC ACCURACY CURVES POWER REQUIREMENT CURVES TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS NORMAL MODE POWER CONSUMPTION Power Consumption Example 1 Power Consumption Example 2 SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7466/AD7467/AD7468 to TMS320C541 Interface AD7466/AD7467/AD7468 to ADSP-218x Interface AD7466/AD7467/AD7468 to DSP563xx Interface APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE PERFORMANCE OF THE AD7466 AND AD7467 OUTLINE DIMENSIONS ORDERING GUIDE
