Datasheet AD9244 (Analog Devices) - 9

AD9244 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS – + FT FT FB FB FGND EF VR VIN VIN CML NIC DCS RE RE RE RE RE VR 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 SENSE PIN 1 AGND 2 35 DFS AVDD 3 34 AVDD AVDD 4 33 AGND AGND 5 32 AGND AD9244 CLK– 6 31 TOP VIEW AVDD CLK+ 7 (Not to Scale) 30 DGND NIC 8 29 DRVDD OEB 9 28 OTR D0 (LSB) 10 27 D13 (MSB) D1 11 26 D12 D2 12 25 D11 13 14 15 16 17 18 19 20 21 22 23 24 0 D3 DD D4 D5 D6 D7 D8 D9 DD D1 DGND DGND DRV DRV
02404-003 Figure 3. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
1, 2, 5, 32, 33 AGND Analog Ground. 3, 4, 31, 34 AVDD Analog Supply Voltage. 6, 7 CLK–, CLK+ Differential Clock Inputs. 8, 44 NIC No Internal Connection. 9 OEB Digital Output Enable (Active Low). 10 D0 (LSB) Least Significant Bit, Digital Output. 11 to 13, D1 to D3, Digital Outputs. 16 to 21, D4 to D9, 24 to 26 D10 to D12 14, 22, 30 DGND Digital Ground. 15, 23, 29 DRVDD Digital Supply Voltage. 27 D13 (MSB) Most Significant Bit, Digital Output. 28 OTR Out-of-Range Indicator (Logic 1 Indicates OTR). 35 DFS Data Format Select. Connect to AGND for straight binary, AVDD for twos complement. 36 SENSE Internal Reference Control. 37 VREF Internal Reference. 38 REFGND Reference Ground. 39 to 42 REFB, REFT Internal Reference Decoupling. 43 DCS 50% Duty Cycle Stabilizer. Connect to AVDD to activate 50% duty cycle stabilizer, AGND for external control of both clock edges. 45 CML Common-Mode Reference (0.5 × AVDD). 46, 47 VIN+, VIN– Differential Analog Inputs. 48 VR Internal Bias Decoupling. Rev. C | Page 8 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL APPLICATION CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW ANALOG INPUT OPERATION Single-Ended Input Configuration Differentially Driving the Analog Inputs REFERENCE OPERATION Pin-Programmable Reference Resistor-Programmable Reference Using an External Reference Digital Outputs Data Format Select (DFS) Digital Output Driver Considerations DIGITAL INPUTS AND OUTPUTS Out of Range (OTR) Digital Output Enable Function (OEB) Clock Overview Clock Input Modes Clock Input Considerations Clock Power Dissipation Clock Stabilizer (DCS) Grounding and Decoupling Analog and Digital Grounding Analog Supply Decoupling Digital Supply Decoupling Reference Decoupling CML VR EVALUATION BOARD ANALOG INPUT CONFIGURATION REFERENCE CONFIGURATION CLOCK CONFIGURATION OUTLINE DIMENSIONS ORDERING GUIDE