Datasheet AD7677 (Analog Devices) - 5

AD7677 TIMING SPECIFICATIONS (–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise stated.) Symbol Min Typ Max Unit
Refer to Figures 11 and 12 Convert Pulsewidth t1 5 ns Time Between Conversions t2 1/1.25/1.5 Note 1 µs (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay t3 30 ns BUSY HIGH All Modes Except in t4 0.75/1/1.25 µs Master Serial Read after Convert Mode (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay t5 2 ns End of Conversion to BUSY LOW Delay t6 10 ns Conversion Time t7 0.75/1/1.25 µs (Warp Mode/Normal Mode/Impulse Mode) Acquisition Time t8 250 ns RESET Pulsewidth t9 10 ns Refer to Figures 13, 14, and 15 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t10 0.75/1/1.25 µs (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay t11 45 ns Bus Access Request to DATA Valid t12 40 ns Bus Relinquish Time t13 5 15 ns Refer to Figures 17 and 18 (Master Serial Interface Modes)2 CS LOW to SYNC Valid Delay t14 10 ns CS LOW to Internal SCLK Valid Delay t15 10 ns CS LOW to SDOUT Delay t16 10 ns CNVST LOW to SYNC Delay (Read During Convert) t17 25/275/525 ns (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay3 t18 3 ns Internal SCLK Period3 t19 25 40 ns Internal SCLK HIGH3 t20 12 ns Internal SCLK LOW3 t21 7 ns SDOUT Valid Setup Time3 t22 4 ns SDOUT Valid Hold Time3 t23 2 ns SCLK Last Edge to SYNC Delay3 t24 3 CS HIGH to SYNC HI-Z t25 10 ns CS HIGH to Internal SCLK HI-Z t26 10 ns CS HIGH to SDOUT HI-Z t27 10 ns BUSY HIGH in Master Serial Read After Convert3 t28 See Table I CNVST LOW to SYNC Asserted Delay t29 0.75/1/1.25 µs (Warp Mode/Normal Mode/Impulse Mode) SYNC Deasserted to BUSY LOW Delay t30 25 ns Refer to Figures 19 and 20 (Slave Serial Interface Modes) External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 3 18 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns NOTES 1In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 3In serial master read during convert mode. See Table I for serial master read after convert mode. Specifications subject to change without notice. –4– REV. A Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PulSAR Selection GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS Table I. Serial Clock Timings in Master Read after Convert ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Modes of Operation Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Single to Differential Driver Driver Amplifier Choice Voltage Reference Input Power Supply POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read During Conversion MICROPROCESSOR INTERFACING SPI Interface (MC68HC11) ADSP-21065L in Master Serial Interface APPLICATION HINTS Layout Evaluating the AD7677 Performance OUTLINE DIMENSIONS Revision History