Datasheet AD7782 (Analog Devices) - 9

AD7782 NOISE PERFORMANCE MASTER MODE (MODE = 0)
Table I shows the output rms noise and output peak-to-peak In this mode, SCLK is provided by the AD7782. With CS low, resolution in bits (rounded to the nearest 0.5 LSB) for the two SCLK becomes active when a conversion is complete and generates input voltage ranges. The numbers are typical and generated at twenty four falling and rising edges. The DOUT/RDY pin, which a differential input voltage of 0 V. The peak-to-peak resolution is normally high, goes low to indicate that a conversion is complete. figures represent the resolution for which there will be no code Data is output on the DOUT/RDY pin following the SCLK falling flicker within a six-sigma limit. The output noise comes from edge and is valid on the SCLK rising edge. When the 24-bit word two sources. The first is the electrical noise in the semiconduc- has been output, SCLK idles high until the next conversion is tor devices (device noise) used in the implementation of the complete. DOUT/RDY returns high and will remain high until modulator. Secondly, when the analog input is converted into another conversion is available. It then operates as a RDY signal the digital domain, quantization noise is added. The device again. The part will continue to convert until CS is taken high. noise is at a low level and is independent of frequency. The SCLK and DOUT/RDY are three-stated when CS is taken high. quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source.
SLAVE MODE (MODE = 1)
In slave mode, the SCLK is generated externally. SCLK must
Table I. Typical Output RMS Noise and
idle high between data transfers. With CS low, DOUT/RDY
Peak-to-Peak Resolution vs. Input Range
goes low when a conversion is complete. Twenty four SCLK pulses are needed to transfer the digital word from the AD7782.
Input Range
Twenty four consecutive pulses can be generated or, alterna- ⴞ
160 mV
ⴞ
2.56 V
tively, the data transfer can be split into batches. This is useful Noise (µV) 0.65 2.30 when interfacing to a microcontroller which uses 8-bit transfers. Data is output following the SCLK falling edge and is valid on Peak-to-Peak Resolution (Bits) 16.5 18.5 the SCLK rising edge.
DIGITAL INTERFACE CIRCUIT DESCRIPTION
The AD7782’s serial interface consists of four signals, CS, SCLK,
Analog Input Channels
DOUT/RDY, and MODE. The MODE pin is used to select the The ADC has two fully differential input channels. Pin CH1/CH2 master/slave mode of operation. When the part is configured as is used to select the channels. When CH1/CH2 is low, channel a master, SCLK is an output while SCLK is an input when AIN1(+) – AIN1(–) are selected while channel AIN2(+) – AIN2(–) slave mode is selected. Data transfers take place with respect to are selected when CH1/CH2 is high. When the analog input this SCLK signal. The DOUT/RDY line is used for accessing channel is switched, the settling time of the part must elapse data from the data register. This pin also functions as a RDY before a new valid word is available from the ADC. line. When a conversion is complete, DOUT/RDY goes low to The output of the ADC multiplexer feeds into a high-impedance indicate that data is ready to be read from the AD7782’s data input stage of the buffer amplifier. As a result, the ADC inputs register. It is reset high when a read operation from the data can handle significant source impedances and are tailored for direct register is complete. It also goes high prior to the updating of connection to external resistive-type sensors like strain gages or the output register to indicate when not to read from the device Resistance Temperature Detectors (RTDs). to ensure that a data read is not attempted while the register is The absolute input voltage range on the ADC inputs is restricted being updated. The digital conversion is also output on this pin. to a range between GND + 100 mV and VDD – 100 mV. Care CS is used to select the device and to place the device in standby must be taken in setting up the common-mode voltage and input mode. When CS is taken low, the AD7782 is powered up, the voltage range so that these limits are not exceeded; otherwise PLL locks and the device initiates a conversion on the selected there will be a degradation in linearity and noise performance. channel. The device will continue to convert until CS is taken
Programmable Gain Amplifier
high. When CS is taken high, the AD7782 is placed in standby The output from the buffer on the ADC is applied to the input of mode minimizing the current consumption. The conversion is the on-chip programmable gain amplifier (PGA). The PGA gain aborted, DOUT and SCLK are three-stated and the result in range is programmed via pin RANGE. With an external 2.5 V refer- the data register is lost. ence applied, the PGA can be programmed to have a bipolar range Figure 2 shows the timing diagram for interfacing to the AD7782 of ± 160 mV (RANGE = 0) or ± 2.56 V (RANGE = 1). These with CS used to decode the part. are the ranges that should appear at the input to the on-chip PGA. –8– REV. A