Datasheet AD9218 (Analog Devices)

10-Bit, 40/65/80/105 MSPS 3 V Dual Analog-to-Digital Converter AD9218 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual 10-bit, 40 MSPS, 65 MSPS, 80 MSPS, and 105 MSPS ADC ENCODE A TIMING AD9218 Low power: 275 mW at 105 MSPS per channel On-chip reference and track-and-hold AINA OUTPUT T/H ADC / / D9 300 MHz analog bandwidth each channel REGISTER A TO D0A AINA 10 10 USER SNR = 57 dB @ 41 MHz, Encode = 80 MSPS SELECT NO. 1 REF 1 V p-p or 2 V p-p analog input range each channel INA USER REFOUT REF SELECT NO. 2 3.0 V single-supply operation (2.7 V to 3.6 V) REFINB DATA Power-down mode for single-channel operation FORMAT/ GAIN Twos complement or offset binary output mode AINB T/H ADC / OUTPUT / D9B TO D0B REGISTER Output data alignment mode AINB 10 10 Pin compatible with the 8-bit AD9288 ENCODE B TIMING –75 dBc crosstalk between channels
1 00 1- 00
V V
02
D GND DD APPLICATIONS
Figure 1.
Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes I and Q communications Ultrasound equipment GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD9218 is a dual 10-bit monolithic sampling analog-to- 1. Low Power. Only 275 mW power dissipation per channel digital converter with on-chip track-and-hold circuits. The at 105 MSPS. Other speed grades proportionally scaled product is low cost, low power, and is small and easy to use. The down while maintaining high ac performance. AD9218 operates at a 105 MSPS conversion rate with 2. Pin Compatibility Upgrade. Allows easy migration from 8-bit outstanding dynamic performance over its full operating range. to 10-bit devices. Pin compatible with the 8-bit AD9288 Each channel can be operated independently. dual ADC. The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power 3. Easy to Use. On-chip reference and user controls provide supply and a clock for full operation. No external reference or flexibility in system design. driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate 4. High Performance. Maintains 54 dB SNR at 105 MSPS output power supply pin supports interfacing with 3.3 V or with a Nyquist input. 2.5 V logic. 5. Channel Crosstalk. Very low at –75 dBc. The clock input is TTL/CMOS compatible and the 10-bit digital 6. Fabricated on an Advanced CMOS Process. Available in a outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies. 48-lead low profile quad flat package (7 mm × 7 mm User-selectable options offer a combination of power-down LQFP) specified over the industrial temperature range modes, digital data formats, and digital data timing schemes. (−40°C to +85°C). In power-down mode, the digital outputs are driven to a high impedance state.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD9218 ENCODE INPUT DIGITAL OUTPUTS ANALOG INPUT VOLTAGE REFERENCE TIMING USER SELECT OPTIONS APPLICATION INFORMATION AD9218/AD9288 CUSTOMER PCB BOM EVALUATION BOARD POWER CONNECTOR ANALOG INPUTS VOLTAGE REFERENCE CLOCKING DATA OUTPUTS DATA FORMAT/GAIN TIMING TROUBLESHOOTING OUTLINE DIMENSIONS ORDERING GUIDE