Datasheet AD9218 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter |
| Pages / Page | 29 / 7 — AD9218. SWITCHING SPECIFICATIONS. Table 4. Test. AD9218BST-40/-65. … |
| Revision | C |
| File Format / Size | PDF / 887 Kb |
| Document Language | English |
AD9218. SWITCHING SPECIFICATIONS. Table 4. Test. AD9218BST-40/-65. AD9218BST-80/-105. Parameter. Temp. Level. Min. Typ. Max. Unit
Model Line for this Datasheet
Text Version of Document
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AD9218 SWITCHING SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 4. Test AD9218BST-40/-65 AD9218BST-80/-105 Parameter Temp Level Min Typ Max Min Typ Max Unit
ENCODE INPUT PARAMETERS Maximum Encode Rate Full VI 40/65 80/105 MSPS Minimum Encode Rate Full IV 20/20 20/20 MSPS Encode Pulse Width High (tEH) Full IV 7/6 5/3.8 ns Encode Pulse Width Low (tEL) Full IV 7/6 5/3.8 ns Aperture Delay (tA) 25°C V 2 2 ns Aperture Uncertainty (Jitter) 25°C V 3 3 ps rms DIGITAL OUTPUT PARAMETERS Output Valid Time (t 1 V) Full VI 2.5 2.5 ns Output Propagation Delay (tPD)1 Full VI 4.5 7 4.5 6 ns Output Rise Time (tR) 25°C V 1 1.0 ns Output Fall Time (tF) 25°C V 1.2 1.2 ns Out-of-Range Recovery Time 25°C V 5 5 ns Transient Response Time 25°C V 5 5 ns Recovery Time from Power-Down 25°C V 10 10 Cycles Pipeline Delay Full IV 5 5 Cycles 1 tV and tPD are measured from the 1.5 level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 5 pF or a dc current of ±40 μA. Rise and fall times are measured from 10% to 90%.
TIMING DIAGRAMS SAMPLE N SAMPLE SAMPLE SAMPLE N + 1 N + 5 N + 6 AINA AINB SAMPLE SAMPLE SAMPLE tA N + 2 N + 3 N + 4 tEL tEH 1/fS ENCODE A ENCODE B tPD tV D9A TO D0A DATA N – 5 DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N
02 0 1-
DATA N – 5 DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N
00
D9B TO D0B
02 Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing Rev. C | Page 6 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD9218 ENCODE INPUT DIGITAL OUTPUTS ANALOG INPUT VOLTAGE REFERENCE TIMING USER SELECT OPTIONS APPLICATION INFORMATION AD9218/AD9288 CUSTOMER PCB BOM EVALUATION BOARD POWER CONNECTOR ANALOG INPUTS VOLTAGE REFERENCE CLOCKING DATA OUTPUTS DATA FORMAT/GAIN TIMING TROUBLESHOOTING OUTLINE DIMENSIONS ORDERING GUIDE
AD9218 SWITCHING SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 4. Test AD9218BST-40/-65 AD9218BST-80/-105 Parameter Temp Level Min Typ Max Min Typ Max Unit
ENCODE INPUT PARAMETERS Maximum Encode Rate Full VI 40/65 80/105 MSPS Minimum Encode Rate Full IV 20/20 20/20 MSPS Encode Pulse Width High (tEH) Full IV 7/6 5/3.8 ns Encode Pulse Width Low (tEL) Full IV 7/6 5/3.8 ns Aperture Delay (tA) 25°C V 2 2 ns Aperture Uncertainty (Jitter) 25°C V 3 3 ps rms DIGITAL OUTPUT PARAMETERS Output Valid Time (t 1 V) Full VI 2.5 2.5 ns Output Propagation Delay (tPD)1 Full VI 4.5 7 4.5 6 ns Output Rise Time (tR) 25°C V 1 1.0 ns Output Fall Time (tF) 25°C V 1.2 1.2 ns Out-of-Range Recovery Time 25°C V 5 5 ns Transient Response Time 25°C V 5 5 ns Recovery Time from Power-Down 25°C V 10 10 Cycles Pipeline Delay Full IV 5 5 Cycles 1 tV and tPD are measured from the 1.5 level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 5 pF or a dc current of ±40 μA. Rise and fall times are measured from 10% to 90%.
TIMING DIAGRAMS SAMPLE N SAMPLE SAMPLE SAMPLE N + 1 N + 5 N + 6 AINA AINB SAMPLE SAMPLE SAMPLE tA N + 2 N + 3 N + 4 tEL tEH 1/fS ENCODE A ENCODE B tPD tV D9A TO D0A DATA N – 5 DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N
02 0 1-
DATA N – 5 DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N
00
D9B TO D0B
02 Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing Rev. C | Page 6 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD9218 ENCODE INPUT DIGITAL OUTPUTS ANALOG INPUT VOLTAGE REFERENCE TIMING USER SELECT OPTIONS APPLICATION INFORMATION AD9218/AD9288 CUSTOMER PCB BOM EVALUATION BOARD POWER CONNECTOR ANALOG INPUTS VOLTAGE REFERENCE CLOCKING DATA OUTPUTS DATA FORMAT/GAIN TIMING TROUBLESHOOTING OUTLINE DIMENSIONS ORDERING GUIDE
