Datasheet AD9235 (Analog Devices) - 10

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Data Sheet AD9235 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth (Full Power Bandwidth) Signal-to-Noise and Distortion (SINAD)
1 The analog input frequency at which the spectral power of the The ratio of the rms signal amplitude (set 0.5 dB below full fundamental frequency (as determined by the FFT analysis) is scale) to the rms value of the sum of all other spectral compo- reduced by 3 dB. nents below the Nyquist frequency, including harmonics but excluding dc.
Aperture Delay (tA)
The delay between the 50% point of the rising edge of the clock
Effective Number of Bits (ENOB)
and the instant at which the analog input is sampled. The ENOB for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD
Aperture Jitter (tJ)
using the following formula The sample-to-sample variation in aperture delay. N = (SINAD − 1.76)/6.02
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
Signal-to-Noise Ratio (SNR)
1 negative full scale through positive full scale. The point used as The ratio of the rms signal amplitude (set at 0.5 dB below full negative full scale occurs ½ LSB before the first code transition. scale) to the rms value of the sum of all other spectral compo- Positive full scale is defined as a level 1 ½ LSBs beyond the last nents below the Nyquist frequency, excluding the first six code transition. The deviation is measured from the middle of harmonics and dc. each particular code to the true straight line.
Spurious-Free Dynamic Range (SFDR)
1
Differential Nonlinearity (DNL, No Missing Codes)
The difference in dB between the rms amplitude of the input An ideal ADC exhibits code transitions that are exactly 1 LSB signal and the peak spurious signal. apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that al 4096
Two-Tone SFDR
1 codes must be present over al operating ranges. The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component
Offset Error
may or may not be an IMD product. The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN–. Offset error is defined as the
Clock Pulse Width and Duty Cycle
deviation of the actual transition from that point. Pulse-width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated
Gain Error
performance. Pulse-width low is the minimum time the clock The first code transition should occur at an analog value ½ LSB pulse should be left in the low state. At a given clock rate, these above negative full scale. The last transition should occur at an specifications define an acceptable clock duty cycle. analog value 1 ½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code
Minimum Conversion Rate
transitions and the ideal difference between first and last code The clock rate at which the SNR of the lowest analog signal transitions. frequency drops by no more than 3 dB below the guaranteed limit.
Temperature Drift
The temperature drift for offset error and gain error specifies
Maximum Conversion Rate
the maximum change from the initial (25°C) value to the value The clock rate at which parametric testing is performed. at TMIN or TMAX.
Output Propagation Delay (tPD) Power Supply Rejection Ratio
The delay between the clock logic threshold and the time when The change in ful scale from the value with the supply all bits are within valid logic levels. at the minimum limit to the value with the supply at its
Out-of-Range Recovery Time
maximum limit. The time it takes for the ADC to reacquire the analog input
Total Harmonic Distortion (THD)
1 after a transition from 10% above positive ful scale to 10% The ratio of the rms sum of the first six harmonic components above negative full scale, or from 10% below negative full scale to the rms value of the measured input signal. to 10% below positive full scale. 1 AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. D | Page 9 of 40 Document Outline Specifications DC Specifications Digital Specifications Switching Specifications AC Specifications Absolute Maximum Ratings Explanation of Test Levels ESD Caution Pin Configurations and Function Descriptions Definitions of Specifications Equivalent Circuits Typical Performance Characteristics Applying the AD9235 Theory of Operation Analog Input Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Power Dissipation and Standby Mode Digital Outputs Timing Voltage Reference Internal Reference Connection External Reference Operation Operational Mode Selection TSSOP Evaluation Board LFCSP Evaluation Board Outline Dimensions Ordering Guide