Datasheet AD7475, AD7495 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 1 MSPS, 12-Bit A/D Converter in MSOP-8 or SOIC-8 |
| Pages / Page | 24 / 7 — Data Sheet. AD7475/AD7495. TIMING SPECIFICATIONS1. Table 3. Parameter. … |
| Revision | D |
| File Format / Size | PDF / 436 Kb |
| Document Language | English |
Data Sheet. AD7475/AD7495. TIMING SPECIFICATIONS1. Table 3. Parameter. Limit at TMIN, TMAX. Unit. Description
Model Line for this Datasheet
Text Version of Document
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Data Sheet AD7475/AD7495 TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475), TA = TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
f 2 SCLK 10 kHz min 20 MHz max tCONVERT 16 × tSCLK tSCLK = 1/fSCLK 800 ns max fSCLK = 20 MHz tQUIET 100 ns min Minimum quiet time required between conversions t2 10 ns min CS to SCLK setup time t 3 3 22 ns max Delay from CS until SDATA three-state disabled t 3 4 40 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK low pulse width t6 0.4 tSCLK ns min SCLK high pulse width t7 10 ns min SCLK to data valid hold time t 4 8 10 ns min SCLK falling edge to SDATA high impedance 45 ns max SCLK falling edge to SDATA high impedance t 4 9 20 ns max CS rising edge to SDATA high impedance tPOWER-UP 20 µs max Power-up time from full power-down (AD7475) 650 µs max Power-up time from full power-down (AD7495) 1 Guaranteed by initial characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4 t8 and t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t8 and t9, quoted in the timing characteristics are the true bus relinquish times of the device and are independent of the bus loading. Rev. C | Page 7 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY AD7475 SPECIFICATIONS AD7495 SPECIFICATIONS TIMING EXAMPLE 1 TIMING EXAMPLE 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM Analog Input Digital Inputs VDRIVE Reference Section OPERATING MODES NORMAL MODE PARTIAL POWER-DOWN MODE Power-Up Time FULL POWER-DOWN MODE POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7475/AD7495 TO TMS320C5x/C54x AD7475/AD7495 TO ADSP-21xx AD7475/AD7495 TO DSP56xxx AD7475/AD7495 TO MC68HC16 OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7475/AD7495 TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475), TA = TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
f 2 SCLK 10 kHz min 20 MHz max tCONVERT 16 × tSCLK tSCLK = 1/fSCLK 800 ns max fSCLK = 20 MHz tQUIET 100 ns min Minimum quiet time required between conversions t2 10 ns min CS to SCLK setup time t 3 3 22 ns max Delay from CS until SDATA three-state disabled t 3 4 40 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK low pulse width t6 0.4 tSCLK ns min SCLK high pulse width t7 10 ns min SCLK to data valid hold time t 4 8 10 ns min SCLK falling edge to SDATA high impedance 45 ns max SCLK falling edge to SDATA high impedance t 4 9 20 ns max CS rising edge to SDATA high impedance tPOWER-UP 20 µs max Power-up time from full power-down (AD7475) 650 µs max Power-up time from full power-down (AD7495) 1 Guaranteed by initial characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4 t8 and t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t8 and t9, quoted in the timing characteristics are the true bus relinquish times of the device and are independent of the bus loading. Rev. C | Page 7 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY AD7475 SPECIFICATIONS AD7495 SPECIFICATIONS TIMING EXAMPLE 1 TIMING EXAMPLE 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM Analog Input Digital Inputs VDRIVE Reference Section OPERATING MODES NORMAL MODE PARTIAL POWER-DOWN MODE Power-Up Time FULL POWER-DOWN MODE POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7475/AD7495 TO TMS320C5x/C54x AD7475/AD7495 TO ADSP-21xx AD7475/AD7495 TO DSP56xxx AD7475/AD7495 TO MC68HC16 OUTLINE DIMENSIONS ORDERING GUIDE
