Datasheet AD7898 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 5V, 12-Bit, Serial 220 kSPS ADC in a 8-Lead Package |
| Pages / Page | 17 / 10 — AD7898. –10. –20. –30. –40. –50. THD – dB –60. VDD = VDRIVE = 5.25V. … |
| Revision | A |
| File Format / Size | PDF / 243 Kb |
| Document Language | English |
AD7898. –10. –20. –30. –40. –50. THD – dB –60. VDD = VDRIVE = 5.25V. Table I. Ideal Input/Output Code Table for the AD7898-10/
Model Line for this Datasheet
Text Version of Document
AD7898
Figure 2 shows the analog input section for the AD7898-10 Figure 3 shows a graph of THD versus source impedance for and AD7898-3. The analog input range of the AD7898-10 is different analog input frequencies when using a supply voltage ±10 V into an input resistance of typically 30 kΩ. The analog of 5 V, VDRIVE of 5 V, and sampling at a rate of 220 kSPS. input range of the AD7898-3 is ± 2.5 V into an input resistance Source impedance has a minimal effect on THD because of the of typically 6 kΩ. This input is benign, with no dynamic charg- resistive ladder structure of the input section of the ADC. Figure 4 ing currents, as the resistor stage is followed by a high input shows a graph of THD versus Analog input frequency for vari- impedance stage of the track/hold amplifier. For the AD7898-10, ous supply voltages while sampling at 220 kSPS. R1 = 30 kΩ, R2 = 7.5 kΩ and R3 = 10 kΩ. For the AD7898-3, R1 = R2 = 6.5 kΩ and R3 is open circuit.
0
For the AD7898-10 and AD7898-3, the designed code transi-
–10
tions occur midway between successive LSB values (i.e., 1/2 LSB,
–20
3/2 LSBs, 5/2 LSBs . .). Output coding is twos complement
–30
binary with 1 LSB = FS/4096. For the AD7898-10 1 LSB = 20/ 4096 = 4.88 mV. For the AD7898-3 1 LSB = 5/4096 = 1.22 mV.
–40
The ideal input/output coding for the AD7898-10 and AD7898-3
–50
is shown in Table I.
THD – dB –60 VDD = VDRIVE = 5.25V Table I. Ideal Input/Output Code Table for the AD7898-10/ –70 VDD = VDRIVE = 4.75V AD7898-3 Digital Output –80 Analog Inputl Code Transition –90 VDD = 5.0V, VDRIVE = 3.0V –100
+FSR/2 – 3/2 LSB2 011 . 110 to 011 . 111
10 100 1000
+FSR/2 – 5/2 LSBs 011 . 101 to 011 . 110
INPUT FREQUENCY – kHz
+FSR/2 – 7/2 LSBs 011 . 100 to 011 . 101 Figure 4. THD vs. Analog Input Frequency for Various Supply Voltages AGND + 3/2 LSB 000 . 001 to 000 . 010
Acquisition Time
AGND + 1/2 LSB 000 . 000 to 000 . 001 The track-and-hold amplifier enters its tracking mode on the AGND – 1/2 LSB 111 . 111 to 000 . 000 falling 14th SCLK edge after the CS falling edge for Mode 1 AGND – 3/2 LSB 111 . 110 to 111 . 111 operation. The time required for the track-and-hold amplifier to acquire an input signal will depend on how quickly the 9.1 pF –FSR/2 + 5/2 LSBs 100 . 010 to 100 . 011 sampling capacitance is charged. With zero source impedance –FSR/2 + 3/2 LSBs 100 . 001 to 100 . 010 on the analog input, two SCLK cycles plus t –FSR/2 + 1/2 LSB 100 . 000 to 100 . 001 QUIET will always be sufficient to acquire the signal to the 12-bit level. With an NOTES SCLK frequency of 3.7 MHz, the acquisition time would be 1FSR is full-scale range = 20 V (AD7898-10) and = 5 V (AD7898-3) with 2 × (270 ns) + t REF IN = 2.5 V. QUIET. 21 LSB = FSR/4096 = 4.883 mV (AD7898-10) and 1.22 mV (AD7898-3) with The acquisition time required is calculated using the following REF IN = 2.5 V. formula: t
–60
ACQ = 10 × (RC) where R is the resistance seen by the track-and-hold amplifier
–65
looking back on the input e.g., for AD7898-10 R = 3.75 kΩ and for AD7898-3 R = 3.25 kΩ. The sampling capacitor has a value of 9.1 pF. Theoretical acquisition times would be 340 ns for
–70
AD7898-10, and 295 ns for AD7898-3. These theoretical values do not include tQUIET or track propagation delays in the part,
–75
typical values would be 520 ns for the AD7898-10 and 450 ns
THD – dB fIN = 25k
⍀
f
for the AD7898-3.
–80 IN = 110k
⍀
fIN = 10k
⍀
fIN = 50k
⍀
–85 –90 10 100 1k 10k SOURCE IMPEDANCE –
⍀ Figure 3. THD vs. Source Impedance for Various Analog Input Frequencies REV. A –9– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Relative Accuracy Differential Nonlinearity Positive Full-Scale Error (AD7898-10) Positive Full-Scale Error (AD7898-3) Bipolar Zero Error (AD7898-10, AD7898-3) Negative Full-Scale Error (AD7898-10) Negative Full-Scale Error (AD7898-3) Track/Hold Acquisition Time PSR (Power Supply Rejection) PERFORMANCE CURVES Noise CONVERTER DETAILS CIRCUIT DESCRIPTION Analog Input Section Acquisition Time TYPICAL CONNECTION DIAGRAM VDRIVE Feature Track/Hold Section Reference Input SERIAL INTERFACE OPERATING MODES Mode 0 Operation Mode 1 Operation Mode Selection Power-Down Mode Power-Up Times MICROPROCESSOR/MICROCONTROLLER INTERFACE FOR MODE 0 OPERATION 8x51/L51 to AD7898 Interface 68HC11/L11 to AD7898 Interface ADSP-2103/ADSP-2105 to AD7898 Interface DSP56002/L002 to AD7898 Interface MICROPROCESSOR INTERFACING FOR MODE 1 TMS320C5x/C54x to AD7898 Interface AD7898 to ADSP-21xx Interface AD7898 to DSP56xxx Interface AD7898 to MC68HC16 Interface OUTLINE DIMENSIONS Revision History
Figure 2 shows the analog input section for the AD7898-10 Figure 3 shows a graph of THD versus source impedance for and AD7898-3. The analog input range of the AD7898-10 is different analog input frequencies when using a supply voltage ±10 V into an input resistance of typically 30 kΩ. The analog of 5 V, VDRIVE of 5 V, and sampling at a rate of 220 kSPS. input range of the AD7898-3 is ± 2.5 V into an input resistance Source impedance has a minimal effect on THD because of the of typically 6 kΩ. This input is benign, with no dynamic charg- resistive ladder structure of the input section of the ADC. Figure 4 ing currents, as the resistor stage is followed by a high input shows a graph of THD versus Analog input frequency for vari- impedance stage of the track/hold amplifier. For the AD7898-10, ous supply voltages while sampling at 220 kSPS. R1 = 30 kΩ, R2 = 7.5 kΩ and R3 = 10 kΩ. For the AD7898-3, R1 = R2 = 6.5 kΩ and R3 is open circuit.
0
For the AD7898-10 and AD7898-3, the designed code transi-
–10
tions occur midway between successive LSB values (i.e., 1/2 LSB,
–20
3/2 LSBs, 5/2 LSBs . .). Output coding is twos complement
–30
binary with 1 LSB = FS/4096. For the AD7898-10 1 LSB = 20/ 4096 = 4.88 mV. For the AD7898-3 1 LSB = 5/4096 = 1.22 mV.
–40
The ideal input/output coding for the AD7898-10 and AD7898-3
–50
is shown in Table I.
THD – dB –60 VDD = VDRIVE = 5.25V Table I. Ideal Input/Output Code Table for the AD7898-10/ –70 VDD = VDRIVE = 4.75V AD7898-3 Digital Output –80 Analog Inputl Code Transition –90 VDD = 5.0V, VDRIVE = 3.0V –100
+FSR/2 – 3/2 LSB2 011 . 110 to 011 . 111
10 100 1000
+FSR/2 – 5/2 LSBs 011 . 101 to 011 . 110
INPUT FREQUENCY – kHz
+FSR/2 – 7/2 LSBs 011 . 100 to 011 . 101 Figure 4. THD vs. Analog Input Frequency for Various Supply Voltages AGND + 3/2 LSB 000 . 001 to 000 . 010
Acquisition Time
AGND + 1/2 LSB 000 . 000 to 000 . 001 The track-and-hold amplifier enters its tracking mode on the AGND – 1/2 LSB 111 . 111 to 000 . 000 falling 14th SCLK edge after the CS falling edge for Mode 1 AGND – 3/2 LSB 111 . 110 to 111 . 111 operation. The time required for the track-and-hold amplifier to acquire an input signal will depend on how quickly the 9.1 pF –FSR/2 + 5/2 LSBs 100 . 010 to 100 . 011 sampling capacitance is charged. With zero source impedance –FSR/2 + 3/2 LSBs 100 . 001 to 100 . 010 on the analog input, two SCLK cycles plus t –FSR/2 + 1/2 LSB 100 . 000 to 100 . 001 QUIET will always be sufficient to acquire the signal to the 12-bit level. With an NOTES SCLK frequency of 3.7 MHz, the acquisition time would be 1FSR is full-scale range = 20 V (AD7898-10) and = 5 V (AD7898-3) with 2 × (270 ns) + t REF IN = 2.5 V. QUIET. 21 LSB = FSR/4096 = 4.883 mV (AD7898-10) and 1.22 mV (AD7898-3) with The acquisition time required is calculated using the following REF IN = 2.5 V. formula: t
–60
ACQ = 10 × (RC) where R is the resistance seen by the track-and-hold amplifier
–65
looking back on the input e.g., for AD7898-10 R = 3.75 kΩ and for AD7898-3 R = 3.25 kΩ. The sampling capacitor has a value of 9.1 pF. Theoretical acquisition times would be 340 ns for
–70
AD7898-10, and 295 ns for AD7898-3. These theoretical values do not include tQUIET or track propagation delays in the part,
–75
typical values would be 520 ns for the AD7898-10 and 450 ns
THD – dB fIN = 25k
⍀
f
for the AD7898-3.
–80 IN = 110k
⍀
fIN = 10k
⍀
fIN = 50k
⍀
–85 –90 10 100 1k 10k SOURCE IMPEDANCE –
⍀ Figure 3. THD vs. Source Impedance for Various Analog Input Frequencies REV. A –9– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Relative Accuracy Differential Nonlinearity Positive Full-Scale Error (AD7898-10) Positive Full-Scale Error (AD7898-3) Bipolar Zero Error (AD7898-10, AD7898-3) Negative Full-Scale Error (AD7898-10) Negative Full-Scale Error (AD7898-3) Track/Hold Acquisition Time PSR (Power Supply Rejection) PERFORMANCE CURVES Noise CONVERTER DETAILS CIRCUIT DESCRIPTION Analog Input Section Acquisition Time TYPICAL CONNECTION DIAGRAM VDRIVE Feature Track/Hold Section Reference Input SERIAL INTERFACE OPERATING MODES Mode 0 Operation Mode 1 Operation Mode Selection Power-Down Mode Power-Up Times MICROPROCESSOR/MICROCONTROLLER INTERFACE FOR MODE 0 OPERATION 8x51/L51 to AD7898 Interface 68HC11/L11 to AD7898 Interface ADSP-2103/ADSP-2105 to AD7898 Interface DSP56002/L002 to AD7898 Interface MICROPROCESSOR INTERFACING FOR MODE 1 TMS320C5x/C54x to AD7898 Interface AD7898 to ADSP-21xx Interface AD7898 to DSP56xxx Interface AD7898 to MC68HC16 Interface OUTLINE DIMENSIONS Revision History
