Datasheet AD7476, AD7477, AD7478 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 8-Bit, 1 MSPS, Low Power Successive Approximation ADC Which Operates From A Single 2.35 V to 5.25 V Power Supply |
| Pages / Page | 24 / 8 — AD7476/AD7477/AD7478. Parameter. A Version1,2 S. Version1,2. Unit. Test … |
| Revision | F |
| File Format / Size | PDF / 341 Kb |
| Document Language | English |
AD7476/AD7477/AD7478. Parameter. A Version1,2 S. Version1,2. Unit. Test Conditions/Comments. TIMING SPECIFICATIONS. Table 4. Limit at T
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AD7476/AD7477/AD7478 Parameter A Version1,2 S Version1,2 Unit Test Conditions/Comments
Power Dissipation5 Normal Mode (Operational) 17.5 17.5 mW max VDD = 5 V, fSAMPLE = 1 MSPS 4.8 4.8 mW max VDD = 3 V, fSAMPLE = 1 MSPS Full Power-Down 5 5 μW max VDD = 5 V, SCLK off 1 Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C. 2 Operational from VDD = 2.0 V, with input high voltage, VINH = 1.8 V minimum. 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section.
TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 4. Limit at T
1
MIN, TMAX Parameter
2,3
3 V 5 V Unit Description
f 4 SCLK 10 10 kHz min 20 20 MHz A version max 12 12 MHz B version max tCONVERT 16 × tSCLK 16 × tSCLK tQUIET 50 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 10 10 ns min Minimum CS pulsewidth t2 10 10 ns min CS to SCLK setup time t 5 3 20 20 ns max Delay from CS until SDATA three-state disabled t 5 4 40 20 ns max Data access time after SCLK falling edge, A version 70 20 ns max Data access time after SCLK falling edge, B version t5 0.4 × 0.4 × ns min SCLK low pulsewidth tSCLK tSCLK t6 0.4 × 0.4 × ns min SCLK high pulsewidth tSCLK tSCLK t7 10 10 ns min SCLK to data valid hold time t 6 8 10 10 ns min SCLK falling edge to SDATA high impedance 25 25 ns max SCLK falling edge to SDATA high impedance t 7 POWER-UP 1 1 μs typ Power-up time from full power-down 1 3 V specifications apply from VDD = 2.7 V to 3.6 V for A version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B version; 5 V specifications apply from VDD = 4.75 V to 5.25 V. 2 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 3 Version A timing specifications apply to the AD7477 and AD7478 S version; B version timing specifications apply to the AD7476 S version. 4 Mark/space ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 6 t8 is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, is the true bus relinquish time of the part and is independent of the bus loading. 7 See Power-Up Time section.
200µA IOL TO OUTPUT 1.6V PIN CL 50pF
2 00 4-
200µA IOH
02 01 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. F | Page 8 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7476 SPECIFICATIONS AD7477 SPECIFICATIONS AD7478 SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM Analog Input Digital Input MODES OF OPERATION Normal Mode Power-Down Mode Power-Up Time POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7476/AD7477/AD7478 to TMS320C5x/C54x Interface AD7476/AD7477/AD7478 to ADSP-21xx Interface AD7476/AD7477/AD7478 to DSP56xxx Interface AD7476/AD7477/AD7478 to MC68HC16 Interface OUTLINE DIMENSIONS ORDERING GUIDE
AD7476/AD7477/AD7478 Parameter A Version1,2 S Version1,2 Unit Test Conditions/Comments
Power Dissipation5 Normal Mode (Operational) 17.5 17.5 mW max VDD = 5 V, fSAMPLE = 1 MSPS 4.8 4.8 mW max VDD = 3 V, fSAMPLE = 1 MSPS Full Power-Down 5 5 μW max VDD = 5 V, SCLK off 1 Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C. 2 Operational from VDD = 2.0 V, with input high voltage, VINH = 1.8 V minimum. 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section.
TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 4. Limit at T
1
MIN, TMAX Parameter
2,3
3 V 5 V Unit Description
f 4 SCLK 10 10 kHz min 20 20 MHz A version max 12 12 MHz B version max tCONVERT 16 × tSCLK 16 × tSCLK tQUIET 50 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 10 10 ns min Minimum CS pulsewidth t2 10 10 ns min CS to SCLK setup time t 5 3 20 20 ns max Delay from CS until SDATA three-state disabled t 5 4 40 20 ns max Data access time after SCLK falling edge, A version 70 20 ns max Data access time after SCLK falling edge, B version t5 0.4 × 0.4 × ns min SCLK low pulsewidth tSCLK tSCLK t6 0.4 × 0.4 × ns min SCLK high pulsewidth tSCLK tSCLK t7 10 10 ns min SCLK to data valid hold time t 6 8 10 10 ns min SCLK falling edge to SDATA high impedance 25 25 ns max SCLK falling edge to SDATA high impedance t 7 POWER-UP 1 1 μs typ Power-up time from full power-down 1 3 V specifications apply from VDD = 2.7 V to 3.6 V for A version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B version; 5 V specifications apply from VDD = 4.75 V to 5.25 V. 2 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 3 Version A timing specifications apply to the AD7477 and AD7478 S version; B version timing specifications apply to the AD7476 S version. 4 Mark/space ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 6 t8 is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, is the true bus relinquish time of the part and is independent of the bus loading. 7 See Power-Up Time section.
200µA IOL TO OUTPUT 1.6V PIN CL 50pF
2 00 4-
200µA IOH
02 01 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. F | Page 8 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7476 SPECIFICATIONS AD7477 SPECIFICATIONS AD7478 SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM Analog Input Digital Input MODES OF OPERATION Normal Mode Power-Down Mode Power-Up Time POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7476/AD7477/AD7478 to TMS320C5x/C54x Interface AD7476/AD7477/AD7478 to ADSP-21xx Interface AD7476/AD7477/AD7478 to DSP56xxx Interface AD7476/AD7477/AD7478 to MC68HC16 Interface OUTLINE DIMENSIONS ORDERING GUIDE
