Datasheet AD7863 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Simultaneous Sampling Dual 175 kSPS 14-Bit A/D Converter |
| Pages / Page | 25 / 5 — AD7863. Parameter. A Version. Version. Unit. Test Conditions/Comments |
| Revision | B |
| File Format / Size | PDF / 458 Kb |
| Document Language | English |
AD7863. Parameter. A Version. Version. Unit. Test Conditions/Comments
Model Line for this Datasheet
Text Version of Document
link to page 25 link to page 5 link to page 25 link to page 25 link to page 4 link to page 25 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 14 link to page 9 link to page 12
AD7863 Parameter A Version
1
B Version
1
Unit Test Conditions/Comments
REFERENCE INPUT/OUTPUT REF IN Input Voltage Range 2.375 to 2.625 2.375 to 2.625 V 2.5 V ± 5% REF IN Input Current ±100 ±100 μA max REF OUT Output Voltage 2.5 2.5 V nom REF OUT Error @ 25°C ±10 ±10 mV max REF OUT Error TMIN to TMAX ±20 ±20 mV max REF OUT Temperature Coefficient 25 25 ppm/°C typ LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 V min VDD = 5 V ± 5% Input Low Voltage, VINL 0.8 0.8 V max VDD = 5 V ± 5% Input Current, IIN ±10 ±10 μA max Input Capacitance, C 5 IN 10 10 pF max LOGIC OUTPUTS Output High Voltage, VOH 4.0 4.0 V min ISOURCE = 200 μA Output Low Voltage, VOL 0.4 0.4 V max ISINK = 1.6 mA DB11 to DB0 Floating-State Leakage Current ±10 ±10 μA max Floating-State Capacitance5 10 10 pF max Output Coding AD7863-10, AD7863-3 Twos complement AD7863-2 Straight (natural) binary CONVERSION RATE Conversion Time Mode 1 Operation 5.2 5.2 μs max For both channels Mode 2 Operation6 10.0 10.0 μs max For both channels Track/Hold Acquisition Time4, 7 0.5 0.5 μs max POWER REQUIREMENTS VDD 5 5 V nom ±5% for specified performance IDD Normal Mode (Mode 1) AD7863-10 18 18 mA max AD7863-3 16 16 mA max AD7863-2 11 11 mA max Power-Down Mode (Mode 2) IDD @ 25°C8 20 20 μA max 40 nA typ. Logic inputs = 0 V or VDD Power Dissipation Normal Mode (Mode 1) AD7863-10 94.50 94.50 mW max VDD = 5.25 V, 70 mW typ AD7863-3 84 84 mW max VDD = 5.25 V, 70 mW typ AD7863-2 57.75 57.75 mW max VDD = 5.25 V, 45 mW typ Power-Down Mode @ 25°C 105 105 μW max 210 nW typ, VDD = 5.25 V 1 Temperature ranges are as follows: A Version and B Version, −40°C to +85°C. 2 Sample tested during initial release. 3 Applies to Mode 1 operation. See Operating Modes section. 4 See Terminology section. 5 Sample tested @ 25°C to ensure compliance. 6 This 10 μs includes the wake-up time from standby. This wake-up time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of CONVST, for a narrow CONVST pulse width the conversion time is effectively the wake-up time plus conversion time, 10 μs. This can be seen from Figure 6. Note that if the CONVST pulse width is greater than 5.2 μs, the effective conversion time increases beyond 10 μs. 7 Performance measured through full channel (multiplexer, SHA, and ADC). 8 For best dynamic performance of the AD7863, ATE device testing has to be performed with power supply decoupling in place. In the AD7863 power-down mode of operation, the leakage current associated with these decoupling capacitors is greater than that of the AD7863 supply current. Therefore, the 40 nA typical figure shown is characterized and guaranteed by design figure, which reflects the supply current of the AD7863 without decoupling in place. The maximum figure shown in the Conditions/Comments column reflects the AD7863 with supply decoupling in place—0.1 μF in parallel with 10 μF disc ceramic capacitors on the VDD pin and 2 × 0.1 μF disc ceramic capacitors on the VREF pin, in both cases to the AGND plane. Rev. B | Page 4 of 24 Document Outline FEATURES GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY CONVERTER DETAILS TRACK-AND-HOLD SECTION REFERENCE SECTION CIRCUIT DESCRIPTION ANALOG INPUT SECTION OFFSET AND FULL-SCALE ADJUSTMENT Positive Full-Scale Adjust (−10 Version) Negative Full-Scale Adjust (−10 Version) TIMING AND CONTROL Read Options OPERATING MODES MODE 1 OPERATION Normal Power, High Sampling Performance MODE 2 OPERATION Power-Down, Auto-Sleep After Conversion AD7863 DYNAMIC SPECIFICATIONS SIGNAL-TO-NOISE RATIO (SNR) EFFECTIVE NUMBER OF BITS TOTAL HARMONIC DISTORTION (THD) INTERMODULATION DISTORTION PEAK HARMONIC OR SPURIOUS NOISE DC LINEARITY PLOT POWER CONSIDERATIONS MICROPROCESSOR INTERFACING AD7863 TO ADSP-2100 INTERFACE AD7863 TO ADSP-2101/ADSP-2102 INTERFACE AD7863 TO TMS32010 INTERFACE AD7863 TO TMS320C25 INTERFACE AD7863 TO MC68000 INTERFACE AD7863 TO 80C196 INTERFACE VECTOR MOTOR CONTROL MULTIPLE AD7863S APPLICATIONS HINTS PC BOARD LAYOUT CONSIDERATIONS GROUND PLANES POWER PLANES SUPPLY DECOUPLING OUTLINE DIMENSIONS ORDERING GUIDE
AD7863 Parameter A Version
1
B Version
1
Unit Test Conditions/Comments
REFERENCE INPUT/OUTPUT REF IN Input Voltage Range 2.375 to 2.625 2.375 to 2.625 V 2.5 V ± 5% REF IN Input Current ±100 ±100 μA max REF OUT Output Voltage 2.5 2.5 V nom REF OUT Error @ 25°C ±10 ±10 mV max REF OUT Error TMIN to TMAX ±20 ±20 mV max REF OUT Temperature Coefficient 25 25 ppm/°C typ LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 V min VDD = 5 V ± 5% Input Low Voltage, VINL 0.8 0.8 V max VDD = 5 V ± 5% Input Current, IIN ±10 ±10 μA max Input Capacitance, C 5 IN 10 10 pF max LOGIC OUTPUTS Output High Voltage, VOH 4.0 4.0 V min ISOURCE = 200 μA Output Low Voltage, VOL 0.4 0.4 V max ISINK = 1.6 mA DB11 to DB0 Floating-State Leakage Current ±10 ±10 μA max Floating-State Capacitance5 10 10 pF max Output Coding AD7863-10, AD7863-3 Twos complement AD7863-2 Straight (natural) binary CONVERSION RATE Conversion Time Mode 1 Operation 5.2 5.2 μs max For both channels Mode 2 Operation6 10.0 10.0 μs max For both channels Track/Hold Acquisition Time4, 7 0.5 0.5 μs max POWER REQUIREMENTS VDD 5 5 V nom ±5% for specified performance IDD Normal Mode (Mode 1) AD7863-10 18 18 mA max AD7863-3 16 16 mA max AD7863-2 11 11 mA max Power-Down Mode (Mode 2) IDD @ 25°C8 20 20 μA max 40 nA typ. Logic inputs = 0 V or VDD Power Dissipation Normal Mode (Mode 1) AD7863-10 94.50 94.50 mW max VDD = 5.25 V, 70 mW typ AD7863-3 84 84 mW max VDD = 5.25 V, 70 mW typ AD7863-2 57.75 57.75 mW max VDD = 5.25 V, 45 mW typ Power-Down Mode @ 25°C 105 105 μW max 210 nW typ, VDD = 5.25 V 1 Temperature ranges are as follows: A Version and B Version, −40°C to +85°C. 2 Sample tested during initial release. 3 Applies to Mode 1 operation. See Operating Modes section. 4 See Terminology section. 5 Sample tested @ 25°C to ensure compliance. 6 This 10 μs includes the wake-up time from standby. This wake-up time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of CONVST, for a narrow CONVST pulse width the conversion time is effectively the wake-up time plus conversion time, 10 μs. This can be seen from Figure 6. Note that if the CONVST pulse width is greater than 5.2 μs, the effective conversion time increases beyond 10 μs. 7 Performance measured through full channel (multiplexer, SHA, and ADC). 8 For best dynamic performance of the AD7863, ATE device testing has to be performed with power supply decoupling in place. In the AD7863 power-down mode of operation, the leakage current associated with these decoupling capacitors is greater than that of the AD7863 supply current. Therefore, the 40 nA typical figure shown is characterized and guaranteed by design figure, which reflects the supply current of the AD7863 without decoupling in place. The maximum figure shown in the Conditions/Comments column reflects the AD7863 with supply decoupling in place—0.1 μF in parallel with 10 μF disc ceramic capacitors on the VDD pin and 2 × 0.1 μF disc ceramic capacitors on the VREF pin, in both cases to the AGND plane. Rev. B | Page 4 of 24 Document Outline FEATURES GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY CONVERTER DETAILS TRACK-AND-HOLD SECTION REFERENCE SECTION CIRCUIT DESCRIPTION ANALOG INPUT SECTION OFFSET AND FULL-SCALE ADJUSTMENT Positive Full-Scale Adjust (−10 Version) Negative Full-Scale Adjust (−10 Version) TIMING AND CONTROL Read Options OPERATING MODES MODE 1 OPERATION Normal Power, High Sampling Performance MODE 2 OPERATION Power-Down, Auto-Sleep After Conversion AD7863 DYNAMIC SPECIFICATIONS SIGNAL-TO-NOISE RATIO (SNR) EFFECTIVE NUMBER OF BITS TOTAL HARMONIC DISTORTION (THD) INTERMODULATION DISTORTION PEAK HARMONIC OR SPURIOUS NOISE DC LINEARITY PLOT POWER CONSIDERATIONS MICROPROCESSOR INTERFACING AD7863 TO ADSP-2100 INTERFACE AD7863 TO ADSP-2101/ADSP-2102 INTERFACE AD7863 TO TMS32010 INTERFACE AD7863 TO TMS320C25 INTERFACE AD7863 TO MC68000 INTERFACE AD7863 TO 80C196 INTERFACE VECTOR MOTOR CONTROL MULTIPLE AD7863S APPLICATIONS HINTS PC BOARD LAYOUT CONSIDERATIONS GROUND PLANES POWER PLANES SUPPLY DECOUPLING OUTLINE DIMENSIONS ORDERING GUIDE
