Datasheet AD7863 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Simultaneous Sampling Dual 175 kSPS 14-Bit A/D Converter |
| Pages / Page | 25 / 6 — AD7863. TIMING CHARACTERISTICS. Table 2. Parameter. A, B Versions. Unit. … |
| Revision | B |
| File Format / Size | PDF / 458 Kb |
| Document Language | English |
AD7863. TIMING CHARACTERISTICS. Table 2. Parameter. A, B Versions. Unit. Test Conditions/Comments. tACQ. CONVST. BUSY. tCONV = 5.2µs. DATA
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AD7863 TIMING CHARACTERISTICS
VDD = 5 V ± 5%, AGND = DGND = 0 V, REF = Internal. All specifications TMIN to TMAX, unless otherwise noted.
Table 2. Parameter 1 , 2 A, B Versions Unit Test Conditions/Comments
tCONV 5.2 μs max Conversion time tACQ 0.5 μs max Acquisition time Parallel Interface t1 0 ns min CS to RD setup time t2 0 ns min CS to RD hold time t3 35 ns min CONVST pulse width t4 45 ns min RD pulse width t 3 5 30 ns min Data access time after falling edge of RD t 4 6 5 ns min Bus relinquish time after rising edge of RD 30 ns max t7 10 ns min Time between consecutive reads t8 400 ns min Quiet time 1 Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figure 2. 3 Measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
tACQ t8 CONVST t3 BUSY tCONV = 5.2µs A0 CS t1 t2 t7 t4 RD t5 t6
02
DATA V
0
A1 VA2 VB1 VB2
1- 41 06 Figure 2. Timing Diagram
1.6mA TO OUTPUT PIN 50pF 200µA
03 0 1- 41 06 Figure 3. Load Circuit for Access Time and Bus Relinquish Time Rev. B | Page 5 of 24 Document Outline FEATURES GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY CONVERTER DETAILS TRACK-AND-HOLD SECTION REFERENCE SECTION CIRCUIT DESCRIPTION ANALOG INPUT SECTION OFFSET AND FULL-SCALE ADJUSTMENT Positive Full-Scale Adjust (−10 Version) Negative Full-Scale Adjust (−10 Version) TIMING AND CONTROL Read Options OPERATING MODES MODE 1 OPERATION Normal Power, High Sampling Performance MODE 2 OPERATION Power-Down, Auto-Sleep After Conversion AD7863 DYNAMIC SPECIFICATIONS SIGNAL-TO-NOISE RATIO (SNR) EFFECTIVE NUMBER OF BITS TOTAL HARMONIC DISTORTION (THD) INTERMODULATION DISTORTION PEAK HARMONIC OR SPURIOUS NOISE DC LINEARITY PLOT POWER CONSIDERATIONS MICROPROCESSOR INTERFACING AD7863 TO ADSP-2100 INTERFACE AD7863 TO ADSP-2101/ADSP-2102 INTERFACE AD7863 TO TMS32010 INTERFACE AD7863 TO TMS320C25 INTERFACE AD7863 TO MC68000 INTERFACE AD7863 TO 80C196 INTERFACE VECTOR MOTOR CONTROL MULTIPLE AD7863S APPLICATIONS HINTS PC BOARD LAYOUT CONSIDERATIONS GROUND PLANES POWER PLANES SUPPLY DECOUPLING OUTLINE DIMENSIONS ORDERING GUIDE
AD7863 TIMING CHARACTERISTICS
VDD = 5 V ± 5%, AGND = DGND = 0 V, REF = Internal. All specifications TMIN to TMAX, unless otherwise noted.
Table 2. Parameter 1 , 2 A, B Versions Unit Test Conditions/Comments
tCONV 5.2 μs max Conversion time tACQ 0.5 μs max Acquisition time Parallel Interface t1 0 ns min CS to RD setup time t2 0 ns min CS to RD hold time t3 35 ns min CONVST pulse width t4 45 ns min RD pulse width t 3 5 30 ns min Data access time after falling edge of RD t 4 6 5 ns min Bus relinquish time after rising edge of RD 30 ns max t7 10 ns min Time between consecutive reads t8 400 ns min Quiet time 1 Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figure 2. 3 Measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
tACQ t8 CONVST t3 BUSY tCONV = 5.2µs A0 CS t1 t2 t7 t4 RD t5 t6
02
DATA V
0
A1 VA2 VB1 VB2
1- 41 06 Figure 2. Timing Diagram
1.6mA TO OUTPUT PIN 50pF 200µA
03 0 1- 41 06 Figure 3. Load Circuit for Access Time and Bus Relinquish Time Rev. B | Page 5 of 24 Document Outline FEATURES GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY CONVERTER DETAILS TRACK-AND-HOLD SECTION REFERENCE SECTION CIRCUIT DESCRIPTION ANALOG INPUT SECTION OFFSET AND FULL-SCALE ADJUSTMENT Positive Full-Scale Adjust (−10 Version) Negative Full-Scale Adjust (−10 Version) TIMING AND CONTROL Read Options OPERATING MODES MODE 1 OPERATION Normal Power, High Sampling Performance MODE 2 OPERATION Power-Down, Auto-Sleep After Conversion AD7863 DYNAMIC SPECIFICATIONS SIGNAL-TO-NOISE RATIO (SNR) EFFECTIVE NUMBER OF BITS TOTAL HARMONIC DISTORTION (THD) INTERMODULATION DISTORTION PEAK HARMONIC OR SPURIOUS NOISE DC LINEARITY PLOT POWER CONSIDERATIONS MICROPROCESSOR INTERFACING AD7863 TO ADSP-2100 INTERFACE AD7863 TO ADSP-2101/ADSP-2102 INTERFACE AD7863 TO TMS32010 INTERFACE AD7863 TO TMS320C25 INTERFACE AD7863 TO MC68000 INTERFACE AD7863 TO 80C196 INTERFACE VECTOR MOTOR CONTROL MULTIPLE AD7863S APPLICATIONS HINTS PC BOARD LAYOUT CONSIDERATIONS GROUND PLANES POWER PLANES SUPPLY DECOUPLING OUTLINE DIMENSIONS ORDERING GUIDE
