Datasheet AD7705, AD7706 (Analog Devices) - 6

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AD7705/AD7706 Parameter B Version1 Unit Conditions/Comments
AIN Input Sampling Rate, fS Gain × fCLKIN/64 For gains of 1 to 4 fCLKIN/8 For gains of 8 to 128 Reference Input Range REF IN(+) − REF IN(−) Voltage 1/1.75 V min/V max VDD = 2.7 V to 3.3 V VREF = 1.225 ± 1% for specified performance REF IN(+) − REF IN(−) Voltage 1/3.5 V min/V max VDD = 4.75 V to 5.25 V VREF = 2.5 ± 1% for specified performance REF IN Input Sampling Rate, fS fCLKIN/64 LOGIC INPUTS Input Current All Inputs, Except MCLK IN ±1 μA max Typically ±20 nA MCLK IN ±10 μA max Typically ±2 μA All Inputs, Except SCLK and MCLK IN Input Low Voltage, VINL 0.8 V max VDD = 5 V 0.4 V max VDD = 3 V Input High Voltage, VINH 2.0 V min VDD = 3 V and 5 V SCLK Only (Schmitt-Triggered Input) VDD = 5 V nominal VT+ 1.4/3 V min/V max VT− 0.8/1.4 V min/V max VT+ − VT− 0.4/0.8 V min/V max SCLK Only (Schmitt-Triggered Input) VDD = 3 V nominal VT+ 1/2 V min/V max VT− 0.4/1.1 V min/V max VT+ − VT− 0.375/0.8 V min/V max MCLK IN Only VDD = 5 V nominal Input Low Voltage, VINL 0.8 V max Input High Voltage, VINH 3.5 V min MCLK IN Only VDD = 3 V nominal Input Low Voltage, VINL 0.4 V max Input High Voltage, VINH 2.5 V min LOGIC OUTPUTS (Including MCLK OUT) Output Low Voltage, VOL 0.4 V max ISINK = 800 μA, except for MCLK OUT;13 VDD = 5 V Output Low Voltage, VOL 0.4 V max ISINK = 100 μA, except for MCLK OUT;13 VDD = 3 V Output High Voltage, VOH 4 V min ISOURCE = 200 μA, except for MCLK OUT;13 VDD = 5 V Output High Voltage, VOH VDD − 0.6 V min ISOURCE = 100 μA, except for MCLK OUT;13 VDD = 3 V Floating State Leakage Current ±10 μA max Floating State Output Capacitance14 9 pF typ Data Output Coding Binary Unipolar mode Offset binary Bipolar mode SYSTEM CALIBRATION Positive Full-Scale Limit15 (1.05 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) Negative Full-Scale Limit15 −(1.05 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) Offset Limit15 −(1.05 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) Input Span16 (0.8 × VREF)/gain V min Gain is the selected PGA gain (1 to 128) (2.1 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) Rev. C | Page 6 of 44 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUTPUT NOISE (5 V OPERATION) OUTPUT NOISE (3 V OPERATION) TYPICAL PERFORMANCE CHARACTERISTICS ON-CHIP REGISTERS COMMUNICATION REGISTER (RS2, RS1, RS0 = 0, 0, 0) SETUP REGISTER (RS2, RS1, RS0 = 0, 0, 1); POWER-ON/RESET STATUS: 01 HEXADECIMAL CLOCK REGISTER (RS2, RS1, RS0 = 0, 1, 0); POWER-ON/RESET STATUS: 05 HEXADECIMAL DATA REGISTER (RS2, RS1, RS0 = 0, 1, 1) TEST REGISTER (RS2, RS1, RS0 = 1, 0, 0); POWER-ON/RESET STATUS: 00 HEXADECIMAL ZERO-SCALE CALIBRATION REGISTER (RS2, RS1, RS0 = 1, 1, 0); POWER-ON/RESET STATUS: 1F4000 HEXADECIMAL FULL-SCALE CALIBRATION REGISTER (RS2, RS1, RS0 = 1, 1, 1); POWER-ON/RESET STATUS: 5761AB HEXADECIMAL Calibration Sequences CIRCUIT DESCRIPTION ANALOG INPUT Ranges Sample Rate BIPOLAR/UNIPOLAR INPUT REFERENCE INPUT DIGITAL FILTERING Filter Characteristics Postfiltering ANALOG FILTERING CALIBRATION Self-Calibration System Calibration Span and Offset Limits Power-Up and Calibration THEORY OF OPERATION CLOCKING AND OSCILLATOR CIRCUIT SYSTEM SYNCHRONIZATION RESET INPUT STANDBY MODE ACCURACY DRIFT CONSIDERATIONS POWER SUPPLIES SUPPLY CURRENT GROUNDING AND LAYOUT EVALUATING THE PERFORMANCE DIGITAL INTERFACE CONFIGURING THE AD7705/AD7706 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7705/AD7706-to-68HC11 Interface AD7705/AD7706-to-8051 Interface AD7705/AD7706-to-ADSP-2103/ADSP-2105 Interface CODE FOR SETTING UP THE AD7705/AD7706 C Code for Interfacing AD7705 to 68HC11 APPLICATIONS PRESSURE MEASUREMENT TEMPERATURE MEASUREMENT SMART TRANSMITTERS BATTERY MONITORING OUTLINE DIMENSIONS ORDERING GUIDE