Datasheet AD6640 (Analog Devices) - 12

AD6640 THEORY OF OPERATION
The AD6640 analog-to-digital converter (ADC) employs a two-
ENCODE 5V ENCODE
stage subrange architecture. This design approach ensures
SOURCE R1 V
12-bit accuracy, without the need for laser trim, at low power.
l ENCODE Rx
As shown in the functional block diagram, the AD6640 has
0.01
␮
F R2 AD6640
complementary analog input pins, AIN and AIN. Each analog input is centered at 2.4 V and should swing ± 0.5 V around this reference (see Figure 2). Since AIN and AIN are 180 degrees out Figure 8. Lower Logic Threshold for ENCODE of phase, the differential analog input signal is 2 V p-p. 5R2 V = Both analog inputs are buffered prior to the first track-and-hold, l R R 1 x to raise logic threshold. TH1. The high state of the ENCODE pulse places TH1 in hold R2 + R1+Rx mode. The held value of TH1 is applied to the input of a 6-bit coarse ADC. The digital output of the coarse ADC drives a 6-bit DAC; the DAC is 12 bits accurate. The output of the 6-bit
AVCC
DAC is subtracted from the delayed analog signal at the input
Rx
of TH3 to generate a residue signal. TH2 is used as an analog
ENCODE 5V ENCODE
pipeline to null out the digital delay of the coarse ADC.
SOURCE R1 ENCODE Vl
The 6-bit coarse ADC word and 7-bit residue word are added
R2
together and corrected in the digital error correction logic to
0.01
␮
F AD6640
generate the output word. The result is a 12-bit parallel digital CMOS compatible word, coded as twos complement. Figure 9. Raise Logic Threshold for ENCODE
APPLYING THE AD6640
While the single-ended ENCODE will work well for many appli-
Encoding the AD6640
cations, driving the ENCODE differentially will provide increased A valid ENCODE clock must be present on the AD6640 before performance. Depending on circuit layout and system noise, a 1 dB the application of AVCC (5 V). Best performance is obtained by to 3 dB improvement in SNR can be realized. It is not recom- driving the ENCODE pins differentially. However, the AD6640 mended that differential TTL logic be used because most TTL is also designed to interface with TTL and CMOS logic families. families that support complementary outputs are not delay or The source used to drive the ENCODE pin(s) must be clean slew rate matched. Instead, it is recommended that the ENCODE and free from jitter. Sources with excessive jitter will limit SNR signal be ac-coupled into the ENCODE and ENCODE pins. (see the first equation under the Noise Floor and SNR section). The simplest option is shown below. The low jitter TTL signal is coupled with a limiting resistor, typically 100 Ω, to the primary
AD6640
side of an RF transformer (these transformers are inexpensive
TTL OR CMOS ENCODE
and readily available; part number in Figure 10 is from Mini-
SOURCE
Circuits). The secondary side is connected to the ENCODE
ENCODE
and ENCODE pins of the converter. Since both ENCODE
0.01
␮
F
inputs are self-biased, no additional components are required. Figure 7. Single-Ended TTL /CMOS ENCODE
0.1
␮
F 100
⍀
T1–1T TTL ENCODE
The AD6640 ENCODE inputs are connected to a differential
AD6640
input stage (see Figure 3). With no input signal connected to either ENCODE pin, the voltage dividers bias the inputs to
ENCODE
1.6 V. For TTL or CMOS usage, the ENCODE source should be connected to ENCODE, Pin 3. ENCODE should be decoupled Figure 10. TTL Source–Differential ENCODE using a low inductance or microwave chip capacitor to ground. A clean sine wave may be substituted for a TTL clock. In this If a logic threshold other than the nominal 1.6 V is required, case, the matching network is shown. Select a transformer ratio the following equations show how to use an external resistor, to match source and load impedances. The input impedance of Rx, to raise or lower the trip point (see Figure 3; R1 = 17 kΩ the AD6640 ENCODE is approximately 11 kΩ differentially. and R2 = 8 kΩ). Therefore the “R,” shown in the Figure 11, may be any value that is convenient for available drive power. V = 5R2Rx l to lower logic threshold. R1R2 + R1Rx + R2Rx REV. A –11– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal) Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Power Supply Rejection Ratio Signal-to-Noise-and-Distortion (SINAD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR Worst Harmonic Equivalent Circuits Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD6640 Encoding the AD6640 Driving the Analog Input Power Supplies Output Loading Layout Information Evaluation Boards DIGITAL WIDEBAND RECEIVERS Introduction System Description System Requirements Noise Floor and SNR Processing Gain Overcoming Static Nonlinearities with Dither Receiver Example IF Sampling Using the AD6640 as a Mix-Down Stage RECEIVE CHAIN FOR A PHASED-ARRAY CELLULAR BASE STATION OUTLINE DIMENSIONS Revision History