Datasheet AD6640 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Multi-Channel, Multi-Mode Receiver Chipset |
| Pages / Page | 25 / 6 — AD6640. PIN FUNCTION DESCRIPTIONS. Pin No. Name. Function. PIN … |
| Revision | A |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
AD6640. PIN FUNCTION DESCRIPTIONS. Pin No. Name. Function. PIN CONFIGURATION. (MSB). D11. D10. GND. 44 43 42 41 40 39 38 37 36 35 34. DVCC 1
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Text Version of Document
AD6640 PIN FUNCTION DESCRIPTIONS Pin No. Name Function
1, 2, 36, 37, 40, 41 DVCC 3.3 V/5 V Power Supply (Digital). Powers output stage only. 3 ENCODE Encode Input. Data conversion initiated on rising edge. 4 ENCODE Complement of ENCODE. Drive differentially with ENCODE or bypass to ground for single-ended clock mode. See Encoding the AD6640 section. 5, 6, 13, 14, 17, 18, 21, GND Ground 22, 24, 34, 35, 38, 39 7 AIN Analog Input 8 AIN Complement of Analog Input 9 VREF Internal Voltage Reference. Nominally 2.4 V. Bypass to ground with 0.1 µF + 0.01 µF microwave chip capacitor. 10 C1 Internal Bias Point. Bypass to ground with 0.01 µF capacitor. 11, 12, 15, 16, 19, 20 AVCC 5 V Power Supply (Analog) 23 NC No Connect 25 D0 (LSB) Digital Output Bit (Least Significant Bit) 26–33 D1–D8 Digital Output Bits 42, 43 D9–D10 Digital Output Bits 44 D11 (MSB)* Digital Output Bit (Most Significant Bit) *Output coded as twos complement.
PIN CONFIGURATION (MSB) CC CC CC CC D11 D10 D9 DV DV GND GND DV DV GND GND 44 43 42 41 40 39 38 37 36 35 34 DVCC 1 33 D8 DVCC 2 PIN 1 32 D7 ENCODE 3 31 D6 ENCODE 4 30 D5 GND 5 29 D4 AD6640 GND 6 TOP VIEW 28 D3 (Not to Scale) AIN 7 27 D2 AIN 8 26 D1 V 9 25 REF D0 (LSB) C1 10 24 GND AV 11 23 CC NC 12 13 14 15 16 17 18 19 20 21 22 CC CC CC CC CC AV GND GND AV AV GND GND AV AV GND GND NC = NO CONNECT
REV. A –5– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal) Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Power Supply Rejection Ratio Signal-to-Noise-and-Distortion (SINAD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR Worst Harmonic Equivalent Circuits Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD6640 Encoding the AD6640 Driving the Analog Input Power Supplies Output Loading Layout Information Evaluation Boards DIGITAL WIDEBAND RECEIVERS Introduction System Description System Requirements Noise Floor and SNR Processing Gain Overcoming Static Nonlinearities with Dither Receiver Example IF Sampling Using the AD6640 as a Mix-Down Stage RECEIVE CHAIN FOR A PHASED-ARRAY CELLULAR BASE STATION OUTLINE DIMENSIONS Revision History
1, 2, 36, 37, 40, 41 DVCC 3.3 V/5 V Power Supply (Digital). Powers output stage only. 3 ENCODE Encode Input. Data conversion initiated on rising edge. 4 ENCODE Complement of ENCODE. Drive differentially with ENCODE or bypass to ground for single-ended clock mode. See Encoding the AD6640 section. 5, 6, 13, 14, 17, 18, 21, GND Ground 22, 24, 34, 35, 38, 39 7 AIN Analog Input 8 AIN Complement of Analog Input 9 VREF Internal Voltage Reference. Nominally 2.4 V. Bypass to ground with 0.1 µF + 0.01 µF microwave chip capacitor. 10 C1 Internal Bias Point. Bypass to ground with 0.01 µF capacitor. 11, 12, 15, 16, 19, 20 AVCC 5 V Power Supply (Analog) 23 NC No Connect 25 D0 (LSB) Digital Output Bit (Least Significant Bit) 26–33 D1–D8 Digital Output Bits 42, 43 D9–D10 Digital Output Bits 44 D11 (MSB)* Digital Output Bit (Most Significant Bit) *Output coded as twos complement.
PIN CONFIGURATION (MSB) CC CC CC CC D11 D10 D9 DV DV GND GND DV DV GND GND 44 43 42 41 40 39 38 37 36 35 34 DVCC 1 33 D8 DVCC 2 PIN 1 32 D7 ENCODE 3 31 D6 ENCODE 4 30 D5 GND 5 29 D4 AD6640 GND 6 TOP VIEW 28 D3 (Not to Scale) AIN 7 27 D2 AIN 8 26 D1 V 9 25 REF D0 (LSB) C1 10 24 GND AV 11 23 CC NC 12 13 14 15 16 17 18 19 20 21 22 CC CC CC CC CC AV GND GND AV AV GND GND AV AV GND GND NC = NO CONNECT
REV. A –5– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal) Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Power Supply Rejection Ratio Signal-to-Noise-and-Distortion (SINAD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR Worst Harmonic Equivalent Circuits Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD6640 Encoding the AD6640 Driving the Analog Input Power Supplies Output Loading Layout Information Evaluation Boards DIGITAL WIDEBAND RECEIVERS Introduction System Description System Requirements Noise Floor and SNR Processing Gain Overcoming Static Nonlinearities with Dither Receiver Example IF Sampling Using the AD6640 as a Mix-Down Stage RECEIVE CHAIN FOR A PHASED-ARRAY CELLULAR BASE STATION OUTLINE DIMENSIONS Revision History
