Datasheet AD7721 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | CMOS, 12-/16-Bit, 312.5 kHz/468.75 kHz Sigma-Delta ADC |
| Pages / Page | 17 / 5 — AD7721. (AV. TIMING CHARACTERISTICS1, 2. DD= +5 V. 5%; DVDD= +5 V. 5%; … |
| Revision | A |
| File Format / Size | PDF / 299 Kb |
| Document Language | English |
AD7721. (AV. TIMING CHARACTERISTICS1, 2. DD= +5 V. 5%; DVDD= +5 V. 5%; AGND = DGND = 0 V, REFIN = +2.5 V. unless otherwise noted)
Model Line for this Datasheet
Text Version of Document
AD7721 (AV TIMING CHARACTERISTICS1, 2 DD= +5 V
6
5%; DVDD= +5 V
6
5%; AGND = DGND = 0 V, REFIN = +2.5 V unless otherwise noted) Limit at TMIN, TMAX Parameter (A, S Versions) Units Conditions/Comments Serial Interface
f 3 CLK 100 kHz min Master Clock Frequency 15 MHz max 15 MHz for Specified Performance tCLK LO 0.45 × tCLK ns min Master Clock Input Low Time tCLK HI 0.45 × tCLK ns min Master Clock Input High Time t1 tCLK ns nom DRDY High Time t 4 2 tCLK HI – 10 ns min RFS Low to SCLK Falling Edge Setup Time t3 20 ns max RFS Low to Data Valid Delay t4 tCLK HI ns nom SCLK High Pulse Width t5 tCLK LO ns nom SCLK Low Pulse Width t6 25 ns max SCLK Rising Edge to Data Valid Delay t7 0 ns min RFS to SCLK Falling Edge Hold Time t 5 8 0 ns min Bus Relinquish Time after Rising Edge of RFS 20 ns max t9 32 × tCLK ns nom Period between Consecutive DRDY Rising Edges
Parallel Interface
f 3 CLK 100 kHz min Master Clock Frequency 10 MHz max 10 MHz for Specified Performance tCLK LO 0.45 × tCLK ns min Master Clock Input Low Time tCLK HI 0.45 × tCLK ns min Master Clock Input High Time Read Operation t10 2 × tCLK ns nom DRDY High Time t11 30 ns max Data Access Time after Falling Edge of DRDY t12 32 × tCLK ns nom Period between Consecutive DRDY Rising Edges Write Operation t13 35 ns min WR Pulse Width t14 20 ns min Data Valid to WR High Setup Time t15 0 ns min Data Valid to WR High Hold Time NOTES The timing is measured with a load of 50 pF on SCLK and DRDY. SCLK can be operated with a load capacitance of 50 pF maximum. 1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2All digital outputs are timed with the load circuit below and, except for t 2, are defined as the time required for an output to cross 0.8 V or 2 V, whichever occurs last. 3The AD7721 is production tested with fCLK at 10 MHz for parallel mode operation and at 15 MHz for serial mode operation. However, it is guaranteed by character- ization to operate with CLK frequencies down to 100 kHz. 4t2 is the time from RFS crossing 1.6 V to SCLK crossing 0.8 V. 5t8 and t15 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown below. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus relinquish time of the part and, as such, is independent of external bus loading capacitance.
1.6mA IOL TO OUTPUT +1.6V PIN CL 50pF 200 I
m
A OH
Figure 1. Load Circuit for Access Time and Bus Relinquish Time –4– REV. A
6
5%; DVDD= +5 V
6
5%; AGND = DGND = 0 V, REFIN = +2.5 V unless otherwise noted) Limit at TMIN, TMAX Parameter (A, S Versions) Units Conditions/Comments Serial Interface
f 3 CLK 100 kHz min Master Clock Frequency 15 MHz max 15 MHz for Specified Performance tCLK LO 0.45 × tCLK ns min Master Clock Input Low Time tCLK HI 0.45 × tCLK ns min Master Clock Input High Time t1 tCLK ns nom DRDY High Time t 4 2 tCLK HI – 10 ns min RFS Low to SCLK Falling Edge Setup Time t3 20 ns max RFS Low to Data Valid Delay t4 tCLK HI ns nom SCLK High Pulse Width t5 tCLK LO ns nom SCLK Low Pulse Width t6 25 ns max SCLK Rising Edge to Data Valid Delay t7 0 ns min RFS to SCLK Falling Edge Hold Time t 5 8 0 ns min Bus Relinquish Time after Rising Edge of RFS 20 ns max t9 32 × tCLK ns nom Period between Consecutive DRDY Rising Edges
Parallel Interface
f 3 CLK 100 kHz min Master Clock Frequency 10 MHz max 10 MHz for Specified Performance tCLK LO 0.45 × tCLK ns min Master Clock Input Low Time tCLK HI 0.45 × tCLK ns min Master Clock Input High Time Read Operation t10 2 × tCLK ns nom DRDY High Time t11 30 ns max Data Access Time after Falling Edge of DRDY t12 32 × tCLK ns nom Period between Consecutive DRDY Rising Edges Write Operation t13 35 ns min WR Pulse Width t14 20 ns min Data Valid to WR High Setup Time t15 0 ns min Data Valid to WR High Hold Time NOTES The timing is measured with a load of 50 pF on SCLK and DRDY. SCLK can be operated with a load capacitance of 50 pF maximum. 1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2All digital outputs are timed with the load circuit below and, except for t 2, are defined as the time required for an output to cross 0.8 V or 2 V, whichever occurs last. 3The AD7721 is production tested with fCLK at 10 MHz for parallel mode operation and at 15 MHz for serial mode operation. However, it is guaranteed by character- ization to operate with CLK frequencies down to 100 kHz. 4t2 is the time from RFS crossing 1.6 V to SCLK crossing 0.8 V. 5t8 and t15 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown below. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus relinquish time of the part and, as such, is independent of external bus loading capacitance.
1.6mA IOL TO OUTPUT +1.6V PIN CL 50pF 200 I
m
A OH
Figure 1. Load Circuit for Access Time and Bus Relinquish Time –4– REV. A
