Datasheet AD7896 (Analog Devices) - 9

AD7896 OPERATING MODES
before the next conversion takes place. This is achieved by
Mode 1 Operation (High Sampling Performance)
keeping CONVST low at the end of conversion, whereas it was The timing diagram in Figure 2 is for optimum performance in high at the end of conversion for Mode 1 operation. The rising Operating Mode 1 where the falling edge of CONVST starts the edge of CONVST “wakes up” the part. This wake-up time is 6 conversion and puts the track-and-hold amplifier into its hold µs, at which point the track-and-hold amplifier goes into its hold mode. This falling edge of CONVST also causes the BUSY mode. The conversion takes 8 µs after this, provided the signal to go high to indicate that a conversion is taking place. CONVST has gone low, giving a total of 14 µs from the rising The BUSY signal goes low when the conversion is complete, edge of CONVST to the conversion being complete, which is which is 8 µs max after the falling edge of CONVST, and new indicated by the BUSY going low. Note that since the wake- data from this conversion is available in the output register of up time from the rising edge of CONVST is 6 µs, when the the AD7896. A read operation accesses this data. This read CONVST pulsewidth is greater than 6 µs, the conversion will operation consists of 16 clock cycles, and the length of this read take more than the 14 µs shown in the diagram from the rising operation depends on the serial clock frequency. For the fastest edge of CONVST. This is because the track-and-hold amplifier throughput rate (with a serial clock of 10 MHz at 5 V opera- goes into its hold mode on the falling edge of CONVST and tion), the read operation will take 1.6 µs. The read operation then the conversion will not be complete for a further 8 µs. In must be complete at least 400 ns before the falling edge of this case, the BUSY will be the best indicator for when the the next CONVST, which gives a total time of 10 µs for the full conversion is complete. Even though the part is in sleep mode, throughput time (equivalent to 100 kHz). This mode of opera- data can still be read from the part. The read operation consists tion should be used for high sampling applications. of 16 clock cycles as in Mode 1 operation. For the fastest serial clock of 10 MHz at 5 V operation, the read operation will take
Mode 2 Operation (Auto Sleep after Conversion)
The timing diagram in Figure 3 is for optimum performance in 1.6 µs, which must be complete at least 400 ns before the falling Operating Mode 2 where the part automatically goes into sleep edge of the next CONVST to allow the track-and-hold amplifier mode once BUSY goes low after conversion and “wakes up” to have enough time to settle. This mode is very useful when the part is converting at a slow rate as the power consumption will be significantly reduced from that of Mode 1 operation.
tCONVERT = 8
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s t t1 = 40ns MIN 1 CONVST BUSY 400ns MIN SCLK tCONVERT = 8
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s CONVERSION IS CONVERSION ENDS SERIAL READ READ OPERATION OUTPUT INITIATED AND 8
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s LATER OPERATION SHOULD END 400ns SERIAL TRACK-AND-HOLD GOES PRIOR TO NEXT SHIFT INTO HOLD FALLING EDGE OF REGISTER CONVST IS RESET
Figure 2. Mode 1 Timing Operation Diagram for High Sampling Performance
t1 = 6
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s WAKE-UP t1 TIME CONVST BUSY 400ns MIN SCLK tCONVERT = 14
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s PART CONVERSION CONVERSION SERIAL READ READ OPERATION OUTPUT WAKES IS INITIATED ENDS OPERATION SHOULD END 400ns SERIAL UP TRACK-AND- 14µs LATER PRIOR TO NEXT SHIFT HOLD GOES FALLING EDGE OF REGISTER INTO HOLD CONVST IS RESET
Figure 3. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated –8– Rev. D Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Relative Accuracy Differential Nonlinearity Unipolar Offset Error Positive Full-Scale Error Track-and-Hold Acquisition Time Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion CONVERTER DETAILS CIRCUIT DESCRIPTION Analog Input Section Track-and-Hold Section Timing and Control OPERATING MODES Mode 1 Operation (High Sampling Performance) Mode 2 Operation (Auto Sleep after Conversion) Serial Interface MICROPROCESSOR/MICROCONTROLLER INTERFACE AD7896–8051 Interface AD7896–68HC11/L11 Interface AD7896–ADSP-2103/ADSP-2105 Interface AD7896–DSP56002/L002 Interface AD7896 PERFORMANCE Linearity Noise Dynamic Performance (Mode 1 Only) Effective Number of Bits Power Considerations OUTLINE DIMENSIONS ORDERING GUIDE Revision History