Datasheet AD7896 (Analog Devices) - 10

AD7896 Serial Interface
must be low when CONVST goes low in order to reset the The serial interface to the AD7896 consists of three wires: a output shift register correctly. serial clock input (SCLK), the serial data output (SDATA), and The serial clock input does not need to be continuous during a conversion status output (BUSY). This allows for an easy-to- the serial read operation. The 16 bits of data (four leading zeros use interface to most microcontrollers, DSP processors, and and 12-bit conversion result) can be read from the AD7896 in a shift registers. number of bytes. However, the SCLK input must remain low Figure 4 shows the timing diagram for the read operation to the between the two bytes. AD7896. The serial clock input (SCLK) provides the clock The maximum SCLK frequency is 10 MHz for 5 V operation source for the serial interface. Serial data is clocked out from the (giving a throughput of 100 kHz) and at 2.7 V the maximum SDATA line on the falling edge of this clock and is valid on both SCLK frequency is less than 10 MHz to allow for the longer the rising and falling edges of SCLK. The advantage of having data access time, t the data valid on both the rising and falling edges of the SCLK 4 (60 ns @ 5 V, 100 ns @ 2.7 V (A, B, J versions), 70 ns @ 5 V, 110 ns @ 2.7 V (S version)). Note that is to give the user greater flexibility in interfacing to the part and at 3.0 V operation (A, B, J versions), an SCLK of 10 MHz so that a wider range of microprocessor and microcontroller inter- (throughput rate of 100 kHz) may be acceptable if the required faces can be accommodated. This also explains the two timing processor setup time is 0 ns (this may be possible with an ASIC figures t4 and t5 that are quoted on the diagram. The time t4 speci- or FPGA). The data must be read in the next 10 ns, which is fies how long after the falling edge of the SCLK that the next data specified as the data hold time, t bit becomes valid, whereas the time t 5, after the SCLK edge. 5 specifies how long after the falling edge of the SCLK that the current data bit is valid for. The The AD7896 counts the serial clock edges to know which bit first leading zero is clocked out on the first rising edge of from the output register should be placed on the SDATA out- SCLK; note that the first zero may be valid on the first falling put. To ensure that the part does not lose synchronization, the edge of SCLK even though the data access time is specified serial clock counter is reset on the falling edge of the CONVST at 60 ns (5 V [A, B, J versions only]) for the other bits (and the input provided the SCLK line is low. The user should ensure SCLK high time will be 50 ns with a 10 MHz SCLK). The reason that a falling edge on the CONVST input does not occur while that the first bit will be clocked out faster than the other bits is a serial data read operation is in progress. due to the internal architecture of the part. Sixteen clock pulses must be provided to the part to access the full conversion result.
MICROPROCESSOR/MICROCONTROLLER INTERFACE
The AD7896 provides a 3-wire serial interface that can be The AD7896 provides four leading zeros followed by the 12-bit used for connection to the serial ports of DSP processors and conversion result starting with the MSB (DB11). The last data microcontrollers. Figures 5 through 8 show the AD7896 bit to be clocked out on the penultimate falling clock edge is the interfaced to a number of different microcontrollers and DSP LSB (DB0). On the 16th falling edge of SCLK, the LSB (DB0) processors. The AD7896 accepts an external serial clock and as will be valid for a specified time to allow the bit to be read on a result, in all interfaces shown here, the processor/controller is the falling edge of SCLK, and then the SDATA line is disabled configured as the master, providing the serial clock, with the (three-stated). After this last bit has been clocked out, the SCLK AD7896 configured as the slave in the system. input should remain low until the next serial data read opera- tion. If there are extra clock pulses after the 16th clock, the
AD7896–8051 Interface
AD7896 will start over again with outputting data from its out- Figure 5 shows an interface between the AD7896 and the put register, and the data bus will no longer be three-stated even 8X51/L51 microcontroller. The 8X51/L51 is configured for its when the clock stops. Provided the serial clock has stopped Mode 0 serial interface mode. The diagram shows the simplest before the next falling edge of CONVST, the AD7896 will form of the interface where the AD7896 is the only part connected continue to operate correctly with the output shift register being to the serial port of the 8X51/L51 and, therefore, no decoding reset on the falling edge of CONVST. However, the SCLK line of the serial read operations is required.
t2 = t3 = 40ns MIN, t4 = 60ns MAX, t5 = 10ns MIN, t6 = 50ns MAX @ 5V, A, B, VERSIONS t2 SCLK (I/P) 1 2 3 4 5 6 15 16 t3 t5 t t 6 4 THREE-STATE 4 LEADING ZEROS THREE-STATE DOUT (O/P) DB11 DB10 DB0
Figure 4. Data Read Operation Rev. D –9– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Relative Accuracy Differential Nonlinearity Unipolar Offset Error Positive Full-Scale Error Track-and-Hold Acquisition Time Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion CONVERTER DETAILS CIRCUIT DESCRIPTION Analog Input Section Track-and-Hold Section Timing and Control OPERATING MODES Mode 1 Operation (High Sampling Performance) Mode 2 Operation (Auto Sleep after Conversion) Serial Interface MICROPROCESSOR/MICROCONTROLLER INTERFACE AD7896–8051 Interface AD7896–68HC11/L11 Interface AD7896–ADSP-2103/ADSP-2105 Interface AD7896–DSP56002/L002 Interface AD7896 PERFORMANCE Linearity Noise Dynamic Performance (Mode 1 Only) Effective Number of Bits Power Considerations OUTLINE DIMENSIONS ORDERING GUIDE Revision History