Datasheet AD7711 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with Matched RTD Excitation Currents |
| Pages / Page | 29 / 7 — AD7711. TIMING CHARACTERISTICS. Limit at TMIN, TMAX. Parameter. (A, S … |
| Revision | G |
| File Format / Size | PDF / 358 Kb |
| Document Language | English |
AD7711. TIMING CHARACTERISTICS. Limit at TMIN, TMAX. Parameter. (A, S Versions). Unit. Conditions/Comments. PIN CONFIGURATION
Model Line for this Datasheet
Text Version of Document
AD7711 TIMING CHARACTERISTICS Limit at TMIN, TMAX Parameter (A, S Versions) Unit Conditions/Comments
External Clocking Mode fSCLK fCLK IN/5 MHz max Serial Clock Input Frequency t20 0 ns min DRDY to RFS Setup Time t21 0 ns min DRDY to RFS Hold Time t22 2 ¥ tCLK IN ns min A0 to RFS Setup Time t23 0 ns min A0 to RFS Hold Time t 7 24 4 ¥ tCLK IN ns max Data Access Time (RFS Low to Data Valid) t 7 25 10 ns min SCLK Falling Edge to Data Valid Delay 2 ¥ tCLK IN + 20 ns max t26 2 ¥ tCLK IN ns min SCLK High Pulse Width t27 2 ¥ tCLK IN ns min SCLK Low Pulse Width t28 tCLK IN + 10 ns max SCLK Falling Edge to DRDY High t 8 29 10 ns min SCLK to Data Valid Hold Time tCLK IN + 10 ns max t30 10 ns min RFS/TFS to SCLK Falling Edge Hold Time t 8 31 5 ¥ tCLK IN/2 + 50 ns max RFS to Data Valid Hold Time t32 0 ns min A0 to TFS Setup Time t33 0 ns min A0 to TFS Hold Time t34 4 ¥ tCLK IN ns min SCLK Falling Edge to TFS Hold Time t35 2 ¥ tCLK IN – SCLK High ns min Data Valid to SCLK Setup Time t36 30 ns min Data Valid to SCLK Hold Time NOTES 8These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. Specifications subject to change without notice.
PIN CONFIGURATION DIP AND SOIC 1.6mA SCLK 1 24 DGND MCLK IN 2 23 DVDD TO OUTPUT MCLK OUT 3 22 SDATA +2.1V PIN 100pF A0 4 21 DRDY 5 20 SYNC RFS AD7711 200
A MODE 6 TOP VIEW 19 TFS (Not to Scale) AIN1(+) 7 18 AGND
Figure 1. Load Circuit for Access Time and Bus
AIN1(–) 8 17 AIN2
Relinquish Time
RTD1 9 16 REF OUT RTD2 10 15 REF IN(+) V 11 14 SS REF IN(–) AV 12 13 DD VBIAS
–6– REV. G Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING CHARACTERISTICS PIN FUNCTION DESCRIPTIONS TERMINOLOGY Intergral Nonlinearity Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span CONTROL REGISTER (24 BITS) FILTER SELECTION (FS11–FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burnout Current RTD Excitation Current Bipolar/Unipolar Inputs REFERENCE INPUT/OUTPUT VBIAS Input USING THE AD7711 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7711 to 8051 Interface AD7711 to 68HC11 Interface APPLICATIONS 4-Wire RTD Configurations 3-Wire RTD Configurations OUTLINE DIMENSIONS Revision History
External Clocking Mode fSCLK fCLK IN/5 MHz max Serial Clock Input Frequency t20 0 ns min DRDY to RFS Setup Time t21 0 ns min DRDY to RFS Hold Time t22 2 ¥ tCLK IN ns min A0 to RFS Setup Time t23 0 ns min A0 to RFS Hold Time t 7 24 4 ¥ tCLK IN ns max Data Access Time (RFS Low to Data Valid) t 7 25 10 ns min SCLK Falling Edge to Data Valid Delay 2 ¥ tCLK IN + 20 ns max t26 2 ¥ tCLK IN ns min SCLK High Pulse Width t27 2 ¥ tCLK IN ns min SCLK Low Pulse Width t28 tCLK IN + 10 ns max SCLK Falling Edge to DRDY High t 8 29 10 ns min SCLK to Data Valid Hold Time tCLK IN + 10 ns max t30 10 ns min RFS/TFS to SCLK Falling Edge Hold Time t 8 31 5 ¥ tCLK IN/2 + 50 ns max RFS to Data Valid Hold Time t32 0 ns min A0 to TFS Setup Time t33 0 ns min A0 to TFS Hold Time t34 4 ¥ tCLK IN ns min SCLK Falling Edge to TFS Hold Time t35 2 ¥ tCLK IN – SCLK High ns min Data Valid to SCLK Setup Time t36 30 ns min Data Valid to SCLK Hold Time NOTES 8These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. Specifications subject to change without notice.
PIN CONFIGURATION DIP AND SOIC 1.6mA SCLK 1 24 DGND MCLK IN 2 23 DVDD TO OUTPUT MCLK OUT 3 22 SDATA +2.1V PIN 100pF A0 4 21 DRDY 5 20 SYNC RFS AD7711 200
A MODE 6 TOP VIEW 19 TFS (Not to Scale) AIN1(+) 7 18 AGND
Figure 1. Load Circuit for Access Time and Bus
AIN1(–) 8 17 AIN2
Relinquish Time
RTD1 9 16 REF OUT RTD2 10 15 REF IN(+) V 11 14 SS REF IN(–) AV 12 13 DD VBIAS
–6– REV. G Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING CHARACTERISTICS PIN FUNCTION DESCRIPTIONS TERMINOLOGY Intergral Nonlinearity Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span CONTROL REGISTER (24 BITS) FILTER SELECTION (FS11–FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burnout Current RTD Excitation Current Bipolar/Unipolar Inputs REFERENCE INPUT/OUTPUT VBIAS Input USING THE AD7711 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7711 to 8051 Interface AD7711 to 68HC11 Interface APPLICATIONS 4-Wire RTD Configurations 3-Wire RTD Configurations OUTLINE DIMENSIONS Revision History
