Datasheet AD7703 (Analog Devices) - 9

AD7703 DIGITAL FILTERING
The output settling of the AD7703 in response to a step input The AD7703’s digital filter behaves like an analog filter, with a change is shown in Figure 10. The Gaussian response has fast few minor differences. settling with no overshoot, and the worst-case settling time to First, since digital filtering occurs after the analog-to-digital ±0.0007% is 125 ms with a 4.096 MHz master clock frequency. conversion, it can remove noise injected during the conversion process. Analog filtering cannot do this. On the other hand, analog filtering can remove noise superim-
100
posed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near
80
full scale have the potential to saturate the analog modulator and
ALUE V
digital filter, even though the average value of the signal is within
60
limits. To alleviate this problem, the AD7703 has overrange headroom built into the ⌺-⌬ modulator and digital filter that
40
allows overrange excursions of 100 mV. If noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the gain in the input channel so that a full-scale
PERCENT OF FINAL 20
input (2.5 V) gives only a half-scale input to the AD7703 (1.25 V). This will provide an overrange capability greater than 100% at
0
the expense of reducing the dynamic range by one bit (50%).
0 40 80 120 160 TIME – ms FILTER CHARACTERISTICS
Figure 10. AD7703 Step Response The cutoff frequency of the digital filter is fCLK/409600. At the maximum clock frequency of 4.096 MHz, the cutoff frequency
USING THE AD7703
of the filter is 10 Hz and the data update rate is 4 kHz.
SYSTEM DESIGN CONSIDERATIONS
The AD7703 operates differently from successive approximation Figure 9 shows the filter frequency response. This is a six-pole ADCs or integrating ADCs. Since it samples the signal continu- Gaussian response that provides 55 dB of 60 Hz rejection for a ously, like a tracking ADC, there is no need for a start convert 10 Hz cutoff frequency. If the clock frequency is halved to give a command. The 20-bit output register is updated at a 4 kHz rate, 5 Hz cutoff, 60 Hz rejection is better than 90 dB. and the output can be read at any time, either synchronously or asynchronously.
20 0 CLOCKING fCLK = 4MHz
The AD7703 requires a master clock input, which may be an exter-
–20
nal TTL/CMOS compatible clock signal applied to the CLKIN
–40
pin (CLKOUT not used). Alternatively, a crystal of the correct
–60
frequency can be connected between CLKIN and CLKOUT,
fCLK = 2MHz
when the clock circuit will function as a crystal controlled oscillator.
–80 GAIN – dB
Figure 11 shows a simple model of the on-chip gate oscillator
–100
and Table II gives some typical capacitor values to be used with
–120
various resonators.
fCLK = 1MHz –140 R1 –160 5M
⍀
1 10 100 FREQUENCY – Hz 2
Figure 9. Frequency Response of AD7703 Filter
10pF C2* g X1 m = 1500
␮
MHO
Since the AD7703 contains this low-pass filtering, there is a
3
settling time associated with step function inputs, and data will
C1* 10pF
be invalid after a step change until the settling time has elapsed.
AD7703
The AD7703 is, therefore, unsuitable for high speed multiplex-
*SEE TABLE II
ing, where channels are switched and converted sequentially at high rates, as switching between channels can cause a step change Figure 11. On-Chip Gate Oscillator in the input. However, slow multiplexing of the AD7703 is possible, provided that the settling time is allowed to elapse before data for the new channel is accessed. –8– REV. E Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS DEFINITION OF TERMS Linearity Error Differential Linearity Error Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span PIN CONFIGURATION DIP, CERDIP, SOIC PIN FUNCTION DESCRIPTIONS GENERAL DESCRIPTION THEORY OF OPERATION DIGITAL FILTERING FILTER CHARACTERISTICS USING THE AD7703 SYSTEM DESIGN CONSIDERATIONS CLOCKING ANALOG INPUT RANGES ACCURACY AUTOCALIBRATION Initiating Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations INPUT SIGNAL CONDITIONING Source Resistance Antialias Considerations VOLTAGE REFERENCE CONNECTIONS POWER SUPPLIES AND GROUNDING SLEEP MODE DIGITAL INTERFACE Synchronous Self-Clocking Mode (SSC) Synchronous External Clock Mode (SEC) DIGITAL NOISE AND OUTPUT LOADING OUTLINE DIMENSIONS REVISION HISTORY