link to page 19 Data SheetAD8139TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, differential gain = +1, RG = RF = 200 Ω, RL, dm = 1 kΩ, VS = ±5 V, TA = 25°C, VOCM = 0 V. Refer to the basic test circuit in Figure 57 for the definition of terms. 22G = 111G = 1B)0B)0dG = 2d–1N (–1N (G = 5G = 2AI–2AI–2GGP–3P–3OOO–4O–4-L-LD–5D–5EESG = 5–6SO–6OG = 10–7–7D CLG = 10–8D CLE–8EIZ–9IZ–9ALAL–10–10RMRM–11–11NORNORG = 200Ω–12G = 200ΩV–12VO, dm = 0.1V p-pO, dm = 2.0V p-p–13–131101001000 04 07 -0 1101001000 -0 79 79 FREQUENCY (MHz) 46 FREQUENCY (MHz) 46 0 0 Figure 7. Small Signal Frequency Response for Various Gains Figure 10. Large Signal Frequency Response for Various Gains 5342V3S = +5V120)1)B–1Bdd(0(–2INVINV–1S = ±5V–3S = ±5VGA–2GA–4VS = +5VOOP–3OOP–5-L–4-LD–6DEE–5–7OSOSL–6LC–8C–7–9–8–10–9V–11O, dm = 0.1V p-pVO, dm = 2.0V p-p–10–12101001000 05 08 -0 101001000 -0 79 79 FREQUENCY (MHz) 46 FREQUENCY (MHz) 46 0 0 Figure 8. Small Signal Frequency Response for Various Power Supplies Figure 11. Large Signal Frequency Response for Various Power Supplies 33+125°C+125°C+85°C22+85°C1100)–1)B–1Bdd(–2(–2ININ–3–3GA–4GA–4OOP–5OOP–5-L–40°C–6-LD–6DEE–7–7OSOSL–8LC–8C–9–9–40°C+25°C–10–10–11VO, dm = 0.1V p-p–11V+25°CO, dm = 2.0V p-p–12–12101001000 06 09 -0 101001000 -0 79 79 FREQUENCY (MHz) 46 FREQUENCY (MHz) 46 0 0 Figure 9. Small Signal Frequency Response at Various Temperatures Figure 12. Large Signal Frequency Response at Various Temperatures Rev. C | Page 9 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS VS = ±5 V, VOCM = 0 V VS = 5 V, VOCM = 2.5 V ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Maximum Power Dissipation ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION TYPICAL CONNECTION AND DEFINITION OF TERMS Output Balance APPLICATIONS INFORMATION ESTIMATING NOISE, GAIN, AND BANDWIDTH WITH MATCHED FEEDBACK NETWORKS Estimating Output Noise Voltage Voltage Gain Feedback Factor Notation Input Common-Mode Voltage Calculating Input Impedance Input Common-Mode Swing Considerations Bandwidth vs. Closed-Loop Gain Estimating DC Errors Other Impact of Mismatches in the Feedback Networks Driving a Capacitive Load Layout Considerations Terminating a Single-Ended Input Exposed Paddle (EP) OUTLINE DIMENSIONS ORDERING GUIDE