Datasheet AD8421-EP (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 3 nV /√Hz, Low Power Instrumentation Amplifier |
| Pages / Page | 20 / 8 — AD8421-EP. Enhanced Product. TYPICAL PERFORMANCE CHARACTERISTICS. 600. … |
| File Format / Size | PDF / 505 Kb |
| Document Language | English |
AD8421-EP. Enhanced Product. TYPICAL PERFORMANCE CHARACTERISTICS. 600. 500. 400. 300. UNI. 200. 100. –60. –40. –20. –400. –300. –200. –100
Model Line for this Datasheet
Text Version of Document
AD8421-EP Enhanced Product TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15 V, VREF = 0 V, RL = 2 kΩ, unless otherwise noted.
600 600 500 500 400 400 S S T T 300 UNI 300 UNI 200 200 100 100 0 0 –60 –40 –20 0 20 40 60
03 06 0
–400 –300 –200 –100 0 100 200 300 400
0 39- 39-
INPUT OFFSET VOLTAGE (µV)
1 1 1
OUTPUT OFFSET VOLTAGE (µV)
1 1 1 Figure 4. Typical Distribution of Input Offset Voltage Figure 7. Typical Distribution of Output Offset Voltage
1800 1200 1500 1000 1200 800 S T S 900 T 600 UNI UNI 600 400 300 200 0 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
04 0
–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
07 0 39-
INPUT BIAS CURRENT (nA)
1 1 39- 1
INPUT OFFSET CURRENT (nA)
1 1 1 Figure 5. Typical Distribution of Input Bias Current Figure 8. Typical Distribution of Input Offset Current
1600 1400 1400 1200 1200 1000 1000 S T 800 S T 800 UNI UNI 600 600 400 400 200 200 0 0 –20 –15 –10 –5 0 5 10 15 20
05 0
–120 –90 –60 –30 0 30 60 90 120
08 0 39-
PSRR (µV/V)
1 1 39- 1
CMRR (µV/V)
1 1 1 Figure 6. Typical Distribution of PSRR (G = 1) Figure 9. Typical Distribution of CMRR (G = 1) Rev. 0 | Page 8 of 20 Document Outline Features Enhanced Product Features Pin Connection Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide
TA = 25°C, VS = ±15 V, VREF = 0 V, RL = 2 kΩ, unless otherwise noted.
600 600 500 500 400 400 S S T T 300 UNI 300 UNI 200 200 100 100 0 0 –60 –40 –20 0 20 40 60
03 06 0
–400 –300 –200 –100 0 100 200 300 400
0 39- 39-
INPUT OFFSET VOLTAGE (µV)
1 1 1
OUTPUT OFFSET VOLTAGE (µV)
1 1 1 Figure 4. Typical Distribution of Input Offset Voltage Figure 7. Typical Distribution of Output Offset Voltage
1800 1200 1500 1000 1200 800 S T S 900 T 600 UNI UNI 600 400 300 200 0 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
04 0
–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
07 0 39-
INPUT BIAS CURRENT (nA)
1 1 39- 1
INPUT OFFSET CURRENT (nA)
1 1 1 Figure 5. Typical Distribution of Input Bias Current Figure 8. Typical Distribution of Input Offset Current
1600 1400 1400 1200 1200 1000 1000 S T 800 S T 800 UNI UNI 600 600 400 400 200 200 0 0 –20 –15 –10 –5 0 5 10 15 20
05 0
–120 –90 –60 –30 0 30 60 90 120
08 0 39-
PSRR (µV/V)
1 1 39- 1
CMRR (µV/V)
1 1 1 Figure 6. Typical Distribution of PSRR (G = 1) Figure 9. Typical Distribution of CMRR (G = 1) Rev. 0 | Page 8 of 20 Document Outline Features Enhanced Product Features Pin Connection Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide
