AD822015100s)s)µ10µ((SETTLED TO 0.001%EEIMSETTLED TO 0.001%IMTTGG10NNLILISETTLED TO 0.01%TTTTEES5SETTLED TO 0.01%S 43 41 0 0 9- 9- 0 357 357 0 1 0 051015201101001000OUTPUT VOLTAGE STEP SIZE (V)GAIN (V/V) Figure 53. Settling Time vs. Output Voltage Step Size (G = 1) ±15 V, VREF = 0 V Figure 54. Settling Time vs. Gain for a 10 V Step, VS = ±15 V, VREF = 0 V Rev. B | Page 18 of 28 Document Outline Features Applications Pin Configuration General Description Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Gain Selection Layout Common-Mode Rejection Ratio (CMRR) Grounding Reference Terminal Power Supply Regulation and Bypassing Input Bias Current Return Path Input Protection RF Interference Common-Mode Input Voltage Range Driving an ADC Applications Information AC-Coupled Instrumentation Amplifier Differential Output Electrocardiogram Signal Conditioning Outline Dimensions Ordering Guide Automotive Products