Datasheet ADL5500 (Analog Devices) - 22
| Manufacturer | Analog Devices |
| Description | 100 MHz TO 6 GHz TruPwr™ Detector |
| Pages / Page | 26 / 22 — ADL5500. Data Sheet. EVALUATION BOARD. 0.30 mm. (50. 0.20 mm. 0.28 mm. … |
| Revision | B |
| File Format / Size | PDF / 1.8 Mb |
| Document Language | English |
ADL5500. Data Sheet. EVALUATION BOARD. 0.30 mm. (50. 0.20 mm. 0.28 mm. 0.15 mm. VPOS. RFIN. 0.50 mm. 0.38 mm. VRMS. COMM. (PASTE MASK OPENING)
Text Version of Document
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ADL5500 Data Sheet EVALUATION BOARD 0.30 mm (50
Ω
)
Figure 48 shows the schematic of the ADL5500 evaluation board. The layout and silkscreen of the evaluation board layers
0.20 mm 0.28 mm
are shown in Figure 49 to Figure 52. The board is powered by a
0.15 mm
single supply in the 2.7 V to 5.5 V range. The power supply is decoupled by 100 pF and 0.01 µF capacitors. Table 5 details the
VPOS RFIN
various configuration options of the evaluation board.
0.50 mm
Problems caused by impedance mismatch can arise using the
0.50 mm
evaluation board to examine the ADL5500 performance. One way to reduce these problems is to put a coaxial 3 dB attenuator on the RFIN SMA connector. Mismatches at the source, cable,
0.38 mm VRMS COMM (PASTE MASK OPENING)
and cable interconnection, as well as those occurring on the evaluation board, can cause these problems.
GROUND 0.15 mm PLANE
A simple (and common) example of such a problem is triple travel due to mismatch at both the source and the evaluation board. Here the signal from the source reaches the evaluation 05546-054 board and mismatch causes a reflection. When that reflection Figure 47. Land Pattern Used on the ADL5500 Evaluation Board reaches the source mismatch, it causes a new reflection, which travels back to the evaluation board, adding to the original
Junction-to-Board Thermal Impedance
signal incident at the board. The resultant voltage varies with The junction-to-board thermal impedance (θJB) is the thermal both cable length and frequency dependence on the relative impedance from the die to the bottom plane of the four balls of the phase of the initial and reflected signals. Placing the 3 dB pad at ADL5500. For the ADL5500, θJB was determined experimental y to the input of the board improves the match at the board and thus be 56.3°C/W with the device mounted on a 4-layer circuit board reduces the sensitivity to mismatches at the source. When such and two layers being ground planes in a configuration similar to precautions are taken, measurements are less sensitive to cable that of the ADL5500-EVALZ evaluation board. Board size and length and other fixture issues. In an actual application when complexity (number of layers) affect θJB; more layers tend to the distance between ADL5500 and source is short and well- reduce thermal impedance slightly. defined, this 3 dB attenuator is not needed. If the board temperature is known, use the junction-to-board
Land Pattern and Soldering Information
thermal impedance to calculate the die temperature (also known Figure 47 shows the land pattern used on the ADL5500 as junction temperature) to ensure that it does not exceed the evaluation board. Pad diameters of 0.28 mm are used with a specified limit of 125°C. For example, if the board temperature solder paste mask opening of 0.38 mm. For the RF input trace, a is 85°C, the die temperature is given by the equation trace width of 0.30 mm is used, which corresponds to a 50 Ω TJ = TB + (PDISS × θJB) characteristic impedance for the dielectric material being used (FR4). All traces going to the pads are tapered down to 0.15 mm. The worst case power dissipation for the ADL5500 is 58 mW For the RFIN line, the length of the tapered section is 0.20 mm. (5.5 V × 10.5 mA, see Figure 6). Therefore, TJ is TJ = 85°C + (0.058 W × 56.3°C/W) = 88.26°C
TO EDGE CONNECTOR R6 (OPEN) C1 C2 R3 ADL5500 100pF 0.1
µ
F 0
Ω
VRMS 1 VRMS VPOS 4 VPOS C4 R8 10nF (OPEN) 2 COMM RFIN 3 RFIN
05546-044 Figure 48. Evaluation Board Schematic Rev. B | Page 20 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION FILTERING APPLICATIONS INFORMATION BASIC CONNECTIONS OUTPUT SWING LINEARITY INPUT COUPLING USING A SERIES RESISTOR MULTIPLE RF INPUTS SELECTING THE OUTPUT LOW-PASS FILTER NETWORK POWER CONSUMPTION AND POWER-ON/-OFF RESPONSE OUTPUT DRIVE CAPABILITY AND BUFFERING VRMS OUTPUT OFFSET DEVICE CALIBRATION AND ERROR CALCULATION CALIBRATION FOR IMPROVED ACCURACY DRIFT OVER A REDUCED TEMPERATURE RANGE OPERATION ABOVE 4.0 GHz DEVICE HANDLING EVALUATION BOARD Land Pattern and Soldering Information Junction-to-Board Thermal Impedance OUTLINE DIMENSIONS ORDERING GUIDE
ADL5500 Data Sheet EVALUATION BOARD 0.30 mm (50
Ω
)
Figure 48 shows the schematic of the ADL5500 evaluation board. The layout and silkscreen of the evaluation board layers
0.20 mm 0.28 mm
are shown in Figure 49 to Figure 52. The board is powered by a
0.15 mm
single supply in the 2.7 V to 5.5 V range. The power supply is decoupled by 100 pF and 0.01 µF capacitors. Table 5 details the
VPOS RFIN
various configuration options of the evaluation board.
0.50 mm
Problems caused by impedance mismatch can arise using the
0.50 mm
evaluation board to examine the ADL5500 performance. One way to reduce these problems is to put a coaxial 3 dB attenuator on the RFIN SMA connector. Mismatches at the source, cable,
0.38 mm VRMS COMM (PASTE MASK OPENING)
and cable interconnection, as well as those occurring on the evaluation board, can cause these problems.
GROUND 0.15 mm PLANE
A simple (and common) example of such a problem is triple travel due to mismatch at both the source and the evaluation board. Here the signal from the source reaches the evaluation 05546-054 board and mismatch causes a reflection. When that reflection Figure 47. Land Pattern Used on the ADL5500 Evaluation Board reaches the source mismatch, it causes a new reflection, which travels back to the evaluation board, adding to the original
Junction-to-Board Thermal Impedance
signal incident at the board. The resultant voltage varies with The junction-to-board thermal impedance (θJB) is the thermal both cable length and frequency dependence on the relative impedance from the die to the bottom plane of the four balls of the phase of the initial and reflected signals. Placing the 3 dB pad at ADL5500. For the ADL5500, θJB was determined experimental y to the input of the board improves the match at the board and thus be 56.3°C/W with the device mounted on a 4-layer circuit board reduces the sensitivity to mismatches at the source. When such and two layers being ground planes in a configuration similar to precautions are taken, measurements are less sensitive to cable that of the ADL5500-EVALZ evaluation board. Board size and length and other fixture issues. In an actual application when complexity (number of layers) affect θJB; more layers tend to the distance between ADL5500 and source is short and well- reduce thermal impedance slightly. defined, this 3 dB attenuator is not needed. If the board temperature is known, use the junction-to-board
Land Pattern and Soldering Information
thermal impedance to calculate the die temperature (also known Figure 47 shows the land pattern used on the ADL5500 as junction temperature) to ensure that it does not exceed the evaluation board. Pad diameters of 0.28 mm are used with a specified limit of 125°C. For example, if the board temperature solder paste mask opening of 0.38 mm. For the RF input trace, a is 85°C, the die temperature is given by the equation trace width of 0.30 mm is used, which corresponds to a 50 Ω TJ = TB + (PDISS × θJB) characteristic impedance for the dielectric material being used (FR4). All traces going to the pads are tapered down to 0.15 mm. The worst case power dissipation for the ADL5500 is 58 mW For the RFIN line, the length of the tapered section is 0.20 mm. (5.5 V × 10.5 mA, see Figure 6). Therefore, TJ is TJ = 85°C + (0.058 W × 56.3°C/W) = 88.26°C
TO EDGE CONNECTOR R6 (OPEN) C1 C2 R3 ADL5500 100pF 0.1
µ
F 0
Ω
VRMS 1 VRMS VPOS 4 VPOS C4 R8 10nF (OPEN) 2 COMM RFIN 3 RFIN
05546-044 Figure 48. Evaluation Board Schematic Rev. B | Page 20 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION FILTERING APPLICATIONS INFORMATION BASIC CONNECTIONS OUTPUT SWING LINEARITY INPUT COUPLING USING A SERIES RESISTOR MULTIPLE RF INPUTS SELECTING THE OUTPUT LOW-PASS FILTER NETWORK POWER CONSUMPTION AND POWER-ON/-OFF RESPONSE OUTPUT DRIVE CAPABILITY AND BUFFERING VRMS OUTPUT OFFSET DEVICE CALIBRATION AND ERROR CALCULATION CALIBRATION FOR IMPROVED ACCURACY DRIFT OVER A REDUCED TEMPERATURE RANGE OPERATION ABOVE 4.0 GHz DEVICE HANDLING EVALUATION BOARD Land Pattern and Soldering Information Junction-to-Board Thermal Impedance OUTLINE DIMENSIONS ORDERING GUIDE
