Datasheet LTC2321-14 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Dual, 14-Bit + Sign, 2Msps Differential Input ADC with Wide Input Common Mode Range |
| Pages / Page | 28 / 8 — pin FuncTions VDD (Pins 1, 8):. IN2+, AIN2– (Pins 2, 3):. CLKOUT+, … |
| File Format / Size | PDF / 2.6 Mb |
| Document Language | English |
pin FuncTions VDD (Pins 1, 8):. IN2+, AIN2– (Pins 2, 3):. CLKOUT+, CLKOUT– (Pins 17, 18):. GND (Pins 4, 5, 10, 29):
Model Line for this Datasheet
Text Version of Document
link to page 25 LTC2321-14
pin FuncTions VDD (Pins 1, 8):
Power Supply. Bypass VDD to GND with on SDO1+. The logic level is determined by OVDD. Do a 10µF ceramic and a 0.1µF ceramic close to the part. The not connect SDO1–. In LVDS mode, the result is output VDD pins should be shorted together and driven from the differentially on SDO1+ and SDO1–. These pins must be same supply. differentially terminated by an external 100Ω resistor at
A
the receiver (FPGA).
IN2+, AIN2– (Pins 2, 3):
Analog Differential Input Pins. Full-scale range (AIN2+ – AIN2–) is ±REFOUT2 voltage.
CLKOUT+, CLKOUT– (Pins 17, 18):
Serial Data Clock These pins can be driven from VDD to GND. Output. CLKOUT provides a skew-matched clock to latch
GND (Pins 4, 5, 10, 29):
Ground. These pins and exposed the SDO output at the receiver. In CMOS mode, the skew- pad (Pin 29) must be tied directly to a solid ground plane. matched clock is output on CLKOUT+. The logic level is determined by OVDD. Do not connect CLKOUT–. For low
AIN1–, AIN1+ (Pins 6, 7):
Analog Differential Input Pins. throughput applications using SCK to latch the SDO out- Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage. put, CLKOUT+ can be disabled by tying CLKOUT– to OVDD. These pins can be driven from VDD to GND. In LVDS mode, the skew-matched clock is output differ-
CNV (Pin 9):
Conversion Start Input. A fal ing edge on entially on CLKOUT+ and CLKOUT–. These pins must be CNV puts the internal sample-and-hold into the hold mode differentially terminated by an external 100Ω resistor at and starts a conversion cycle. CNV must be driven by a the receiver (FPGA). low jitter clock as shown in the Typical Application circuit
SDO2+, SDO2– (Pins 19, 20):
Channel 2 Serial Data on the back page. The CNV pin is unaffected by the CMOS/ Output. The conversion result is shifted MSB first on each LVDS pin. falling edge of SCK. In CMOS mode, the result is output
REFRTN1 (Pin 11):
Reference Buffer 1 Output Return. on SDO2+. The logic level is determined by OVDD. Do Bypass REFRTN1 to REFOUT1. Do not tie the REFRTN1 not connect SDO2–. In LVDS mode, the result is output pin to the ground plane. differentially on SDO2+ and SDO2–. These pins must be differentially terminated by an external 100Ω resistor at
REFOUT1 (Pin 12):
Reference Buffer 1 Output. An onboard the receiver (FPGA). buffer nominally outputs 4.096V to this pin. This pin is referred to REFRTN1 and should be decoupled closely to
SCK+, SCK– (Pins 21, 22):
Serial Data Clock Input. The the pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor falling edge of this clock shifts the conversion result MSB and a 10μF (X5R, 0805 size) ceramic capacitor in paral- first onto the SDO pins. In CMOS mode, drive SCK+ with lel. The internal buffer driving this pin may be disabled a single-ended clock. The logic level is determined by by grounding the REFINT pin. If the buffer is disabled, OVDD. Do not connect SCK–. In LVDS mode, drive SCK+ an external reference may drive this pin in the range of and SCK–. with a differential clock. These pins must be 1.25V to 5V. differentially terminated by an external 100Ω resistor at the receiver (ADC).
VBYP1 (Pin 13):
Bypass this internally supplied pin to ground with a 1µF ceramic capacitor. The nominal output
OGND (Pin 23):
I/O Ground. This ground must be tied to voltage on this pin is 1.6V. the ground plane at a single point. OVDD is bypassed to this pin.
OVDD (Pin 14):
I/O Interface Digital Power. The range of OV
VBYP2 (Pin 24):
Bypass this internally supplied pin to DD is 1.71V to 2.5V. This supply is nominally set to the same supply as the host interface (CMOS: 1.8V or ground with a 1µF ceramic capacitor. The nominal output 2.5V, LVDS: 2.5V). Bypass OV voltage on this pin is 1.6V DD to OGND with a 0.1μF capacitor.
CMOS/LVDS (Pin 25):
I/O Mode Select. Ground this pin
SDO1+, SDO1– (Pins 15, 16):
Channel 1 Serial Data to enable CMOS mode, tie to OVDD to enable LVDS mode. Output. The conversion result is shifted MSB first on each Float this pin to enable low power LVDS mode. falling edge of SCK. In CMOS mode, the result is output 232114fc 8 For more information www.linear.com/LTC2321-14 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Typical Application Package Description Revision History Related Parts
pin FuncTions VDD (Pins 1, 8):
Power Supply. Bypass VDD to GND with on SDO1+. The logic level is determined by OVDD. Do a 10µF ceramic and a 0.1µF ceramic close to the part. The not connect SDO1–. In LVDS mode, the result is output VDD pins should be shorted together and driven from the differentially on SDO1+ and SDO1–. These pins must be same supply. differentially terminated by an external 100Ω resistor at
A
the receiver (FPGA).
IN2+, AIN2– (Pins 2, 3):
Analog Differential Input Pins. Full-scale range (AIN2+ – AIN2–) is ±REFOUT2 voltage.
CLKOUT+, CLKOUT– (Pins 17, 18):
Serial Data Clock These pins can be driven from VDD to GND. Output. CLKOUT provides a skew-matched clock to latch
GND (Pins 4, 5, 10, 29):
Ground. These pins and exposed the SDO output at the receiver. In CMOS mode, the skew- pad (Pin 29) must be tied directly to a solid ground plane. matched clock is output on CLKOUT+. The logic level is determined by OVDD. Do not connect CLKOUT–. For low
AIN1–, AIN1+ (Pins 6, 7):
Analog Differential Input Pins. throughput applications using SCK to latch the SDO out- Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage. put, CLKOUT+ can be disabled by tying CLKOUT– to OVDD. These pins can be driven from VDD to GND. In LVDS mode, the skew-matched clock is output differ-
CNV (Pin 9):
Conversion Start Input. A fal ing edge on entially on CLKOUT+ and CLKOUT–. These pins must be CNV puts the internal sample-and-hold into the hold mode differentially terminated by an external 100Ω resistor at and starts a conversion cycle. CNV must be driven by a the receiver (FPGA). low jitter clock as shown in the Typical Application circuit
SDO2+, SDO2– (Pins 19, 20):
Channel 2 Serial Data on the back page. The CNV pin is unaffected by the CMOS/ Output. The conversion result is shifted MSB first on each LVDS pin. falling edge of SCK. In CMOS mode, the result is output
REFRTN1 (Pin 11):
Reference Buffer 1 Output Return. on SDO2+. The logic level is determined by OVDD. Do Bypass REFRTN1 to REFOUT1. Do not tie the REFRTN1 not connect SDO2–. In LVDS mode, the result is output pin to the ground plane. differentially on SDO2+ and SDO2–. These pins must be differentially terminated by an external 100Ω resistor at
REFOUT1 (Pin 12):
Reference Buffer 1 Output. An onboard the receiver (FPGA). buffer nominally outputs 4.096V to this pin. This pin is referred to REFRTN1 and should be decoupled closely to
SCK+, SCK– (Pins 21, 22):
Serial Data Clock Input. The the pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor falling edge of this clock shifts the conversion result MSB and a 10μF (X5R, 0805 size) ceramic capacitor in paral- first onto the SDO pins. In CMOS mode, drive SCK+ with lel. The internal buffer driving this pin may be disabled a single-ended clock. The logic level is determined by by grounding the REFINT pin. If the buffer is disabled, OVDD. Do not connect SCK–. In LVDS mode, drive SCK+ an external reference may drive this pin in the range of and SCK–. with a differential clock. These pins must be 1.25V to 5V. differentially terminated by an external 100Ω resistor at the receiver (ADC).
VBYP1 (Pin 13):
Bypass this internally supplied pin to ground with a 1µF ceramic capacitor. The nominal output
OGND (Pin 23):
I/O Ground. This ground must be tied to voltage on this pin is 1.6V. the ground plane at a single point. OVDD is bypassed to this pin.
OVDD (Pin 14):
I/O Interface Digital Power. The range of OV
VBYP2 (Pin 24):
Bypass this internally supplied pin to DD is 1.71V to 2.5V. This supply is nominally set to the same supply as the host interface (CMOS: 1.8V or ground with a 1µF ceramic capacitor. The nominal output 2.5V, LVDS: 2.5V). Bypass OV voltage on this pin is 1.6V DD to OGND with a 0.1μF capacitor.
CMOS/LVDS (Pin 25):
I/O Mode Select. Ground this pin
SDO1+, SDO1– (Pins 15, 16):
Channel 1 Serial Data to enable CMOS mode, tie to OVDD to enable LVDS mode. Output. The conversion result is shifted MSB first on each Float this pin to enable low power LVDS mode. falling edge of SCK. In CMOS mode, the result is output 232114fc 8 For more information www.linear.com/LTC2321-14 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Typical Application Package Description Revision History Related Parts
