Datasheet LTC2321-14 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual, 14-Bit + Sign, 2Msps Differential Input ADC with Wide Input Common Mode Range |
| Pages / Page | 28 / 10 — TiMing DiagraM. applicaTions inForMaTion OVERVIEW. CONVERTER OPERATION |
| File Format / Size | PDF / 2.6 Mb |
| Document Language | English |
TiMing DiagraM. applicaTions inForMaTion OVERVIEW. CONVERTER OPERATION
Model Line for this Datasheet
Text Version of Document
LTC2321-14
TiMing DiagraM
ACQUISITION CONVERSION READOUT CNV 1 2 3 4 5 6 13 14 15 16 SCK HI-Z HI-Z B14 B13 B12 B11 B10 B2 B1 B0 0 SDO CLKOUT 1 2 3 4 5 6 13 14 15 16 SERIAL DATA BITS B[14:0] CORRESPOND TO CURRENT CONVERSION 232114 TD
applicaTions inForMaTion OVERVIEW CONVERTER OPERATION
The LTC2321-14 is a low noise, high speed 14-bit + sign The LTC2321-14 operates in two phases. During the dual successive approximation register (SAR) ADC with acquisition phase, the sample capacitor is connected differential inputs and wide input common mode range. to the analog input pins AIN+ and AIN– to sample the The flexible analog inputs support fully differential, differential analog input voltage, as shown in Figure pseudo-differential bipolar and pseudo-differential uni- 3. A falling edge on the CNV pin initiates a conver- polar drive without requiring any hardware configuration. sion. During the conversion phase, the 15-bit CDAC is The MSB of the 14-bit + sign two’s complement output sequenced through a successive approximation algo- indicates the sign of the differential analog input voltage. rithm, effectively comparing the sampled input with The ADC’s transfer function provides 15-bits of resolu- binary-weighted fractions of the reference voltage tion across the full-scale span of 2 • REFOUT as shown in (e.g., VREFOUT/2, VREFOUT/4 … VREFOUT/16384) using Figure 2. If the analog input spans less than this full-scale, the differential comparator. At the end of conversion, the such as in the case of pseudo-differential drive, the ADC CDAC output approximates the sampled analog input. The provides 14-bits of resolution across this reduced span, ADC control logic then prepares the 15-bit digital output with the additional benefit of digitizing over- and under- code for serial transfer . The data is clocked out on each range conditions, as shown in Table 1. This unique feature falling edge of the SCK+ input clock. is particularly useful in control loop applications. 232114fc 10 For more information www.linear.com/LTC2321-14 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Typical Application Package Description Revision History Related Parts
TiMing DiagraM
ACQUISITION CONVERSION READOUT CNV 1 2 3 4 5 6 13 14 15 16 SCK HI-Z HI-Z B14 B13 B12 B11 B10 B2 B1 B0 0 SDO CLKOUT 1 2 3 4 5 6 13 14 15 16 SERIAL DATA BITS B[14:0] CORRESPOND TO CURRENT CONVERSION 232114 TD
applicaTions inForMaTion OVERVIEW CONVERTER OPERATION
The LTC2321-14 is a low noise, high speed 14-bit + sign The LTC2321-14 operates in two phases. During the dual successive approximation register (SAR) ADC with acquisition phase, the sample capacitor is connected differential inputs and wide input common mode range. to the analog input pins AIN+ and AIN– to sample the The flexible analog inputs support fully differential, differential analog input voltage, as shown in Figure pseudo-differential bipolar and pseudo-differential uni- 3. A falling edge on the CNV pin initiates a conver- polar drive without requiring any hardware configuration. sion. During the conversion phase, the 15-bit CDAC is The MSB of the 14-bit + sign two’s complement output sequenced through a successive approximation algo- indicates the sign of the differential analog input voltage. rithm, effectively comparing the sampled input with The ADC’s transfer function provides 15-bits of resolu- binary-weighted fractions of the reference voltage tion across the full-scale span of 2 • REFOUT as shown in (e.g., VREFOUT/2, VREFOUT/4 … VREFOUT/16384) using Figure 2. If the analog input spans less than this full-scale, the differential comparator. At the end of conversion, the such as in the case of pseudo-differential drive, the ADC CDAC output approximates the sampled analog input. The provides 14-bits of resolution across this reduced span, ADC control logic then prepares the 15-bit digital output with the additional benefit of digitizing over- and under- code for serial transfer . The data is clocked out on each range conditions, as shown in Table 1. This unique feature falling edge of the SCK+ input clock. is particularly useful in control loop applications. 232114fc 10 For more information www.linear.com/LTC2321-14 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Typical Application Package Description Revision History Related Parts
