Datasheet LTC2323-14 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Dual, 14-Bit + Sign, 5Msps Differential Input ADC with Wide Input Common Mode Range |
| Pages / Page | 26 / 8 — PIN FUNCTIONS VDD (Pins 1, 8):. CLKOUT+, CLKOUT– (Pins 17, 18):. AIN2+, … |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
PIN FUNCTIONS VDD (Pins 1, 8):. CLKOUT+, CLKOUT– (Pins 17, 18):. AIN2+, AIN2– (Pins 2, 3):. GND (Pins 4, 5, 10, 29):
Model Line for this Datasheet
Text Version of Document
LTC2323-14
PIN FUNCTIONS VDD (Pins 1, 8):
Power Supply. Bypass VDD to GND with differentially on SDO1+ and SDO1-. These pins must be a 10µF ceramic and a 0.1µF ceramic close to the part. The differentially terminated by an external 100 ohm resistor VDD pins should be shorted together and driven from the at the receiver (FPGA). same supply.
CLKOUT+, CLKOUT– (Pins 17, 18):
Serial Data Clock
AIN2+, AIN2– (Pins 2, 3):
Analog Differential Input Pins. Output. CLKOUT provides a skew-matched clock to latch Full-scale range (AIN2+ – AIN2–) is ±REFOUT2 voltage. the SDO output at the receiver. In CMOS mode, the skew- These pins can be driven from VDD to GND. matched clock is output on CLKOUT+. The logic level
GND (Pins 4, 5, 10, 29):
Ground. These pins and exposed is determined by OVDD. Do not connect CLKOUT–. For pad (Pin 29) must be tied directly to a solid ground plane. low throughput applications using SCK to latch the SDO output, CLKOUT+ can be disabled by tying CLKOUT– to
AIN1–, AIN1+ (Pins 6, 7):
Analog Differential Input Pins. OVDD. In LVDS mode, the skew-matched clock is output Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage. differentially on CLKOUT+ and CLKOUT–. These pins must These pins can be driven from VDD to GND. be differentially terminated by an external 100Ω resistor
CNV (Pin 9):
Conversion Start Input. A falling edge on CNV at the receiver (FPGA). puts the internal sample-and-hold into the hold mode and
SDO2+, SDO2– (Pins 19, 20):
Channel 2 Serial Data Out- starts a conversion cycle. CNV must be driven by a low put. The conversion result is shifted MSB first on each jitter clock as shown in the Typical Application section. falling edge of SCK. In CMOS mode, the result is output The CNV pin is unaffected by the CMOS/LVDS pin. on SDO2+. The logic level is determined by OVDD. Do
REFRTN1 (Pin 11):
Reference Buffer 1 Output Return. not connect SDO2–. In LVDS mode, the result is output Bypass REFRTN1 to REFOUT1. Do not tie the REFRTN1 differentially on SDO2+ and SDO2–. These pins must be pin to the ground plane. differentially terminated by an external 100Ω resistor at the receiver (FPGA).
REFOUT1 (Pin 12):
Reference Buffer 1 Output. An onboard buffer nominally outputs 4.096V to this pin. This pin is re-
SCK+, SCK– (Pins 21, 22):
Serial Data Clock Input. The ferred to REFRTN1 and should be decoupled closely to the falling edge of this clock shifts the conversion result MSB pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor and first onto the SDO pins. In CMOS mode, drive SCK+ with a 10μF (X5R, 0805 size) ceramic capacitor in parallel. The a single-ended clock. The logic level is determined by internal buffer driving this pin may be disabled by ground- OVDD. Do not connect SCK–. In LVDS mode, drive SCK+ ing the REFINT pin. If the buffer is disabled, an external and SCK– with a differential clock. These pins must be reference may drive this pin in the range of 1.25V to 5V. differentially terminated by an external 100Ω resistor at the receiver (ADC).
VBYP1 (Pin 13):
Bypass this internally supplied pin to ground with a 1µF ceramic capacitor. The nominal output
OGND (Pin 23):
I/O Ground. This ground must be tied to voltage on this pin is 1.6V. the ground plane at a single point. OVDD is bypassed to this pin.
OVDD (Pin 14):
I/O Interface Digital Power. The range of OV
VBYP2 (Pin 24):
Bypass this internally supplied pin to DD is 1.71V to 2.5V. This supply is nominally set to the same supply as the host interface (CMOS: 1.8V or 2.5V, ground with a 1µF ceramic capacitor. The nominal output LVDS: 2.5V). Bypass OV voltage on this pin is 1.6V DD to OGND with a 0.1μF capacitor.
SDO1+, SDO1– (Pins 15, 16):
Channel 1 Serial Data Out-
CMOS/LVDS (Pin 25):
I/O Mode Select. Ground this pin put. The conversion result is shifted MSB first on each to enable CMOS mode, tie to OVDD to enable LVDS mode. falling edge of SCK. In CMOS mode, the result is output Float this pin to enable low power LVDS mode. on SDO1+. The logic level is determined by OVDD. Do not connect SDO1–. In LVDS mode, the result is output 232314fb 8 For more information www.linear.com/LTC2323-14 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS VDD (Pins 1, 8):
Power Supply. Bypass VDD to GND with differentially on SDO1+ and SDO1-. These pins must be a 10µF ceramic and a 0.1µF ceramic close to the part. The differentially terminated by an external 100 ohm resistor VDD pins should be shorted together and driven from the at the receiver (FPGA). same supply.
CLKOUT+, CLKOUT– (Pins 17, 18):
Serial Data Clock
AIN2+, AIN2– (Pins 2, 3):
Analog Differential Input Pins. Output. CLKOUT provides a skew-matched clock to latch Full-scale range (AIN2+ – AIN2–) is ±REFOUT2 voltage. the SDO output at the receiver. In CMOS mode, the skew- These pins can be driven from VDD to GND. matched clock is output on CLKOUT+. The logic level
GND (Pins 4, 5, 10, 29):
Ground. These pins and exposed is determined by OVDD. Do not connect CLKOUT–. For pad (Pin 29) must be tied directly to a solid ground plane. low throughput applications using SCK to latch the SDO output, CLKOUT+ can be disabled by tying CLKOUT– to
AIN1–, AIN1+ (Pins 6, 7):
Analog Differential Input Pins. OVDD. In LVDS mode, the skew-matched clock is output Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage. differentially on CLKOUT+ and CLKOUT–. These pins must These pins can be driven from VDD to GND. be differentially terminated by an external 100Ω resistor
CNV (Pin 9):
Conversion Start Input. A falling edge on CNV at the receiver (FPGA). puts the internal sample-and-hold into the hold mode and
SDO2+, SDO2– (Pins 19, 20):
Channel 2 Serial Data Out- starts a conversion cycle. CNV must be driven by a low put. The conversion result is shifted MSB first on each jitter clock as shown in the Typical Application section. falling edge of SCK. In CMOS mode, the result is output The CNV pin is unaffected by the CMOS/LVDS pin. on SDO2+. The logic level is determined by OVDD. Do
REFRTN1 (Pin 11):
Reference Buffer 1 Output Return. not connect SDO2–. In LVDS mode, the result is output Bypass REFRTN1 to REFOUT1. Do not tie the REFRTN1 differentially on SDO2+ and SDO2–. These pins must be pin to the ground plane. differentially terminated by an external 100Ω resistor at the receiver (FPGA).
REFOUT1 (Pin 12):
Reference Buffer 1 Output. An onboard buffer nominally outputs 4.096V to this pin. This pin is re-
SCK+, SCK– (Pins 21, 22):
Serial Data Clock Input. The ferred to REFRTN1 and should be decoupled closely to the falling edge of this clock shifts the conversion result MSB pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor and first onto the SDO pins. In CMOS mode, drive SCK+ with a 10μF (X5R, 0805 size) ceramic capacitor in parallel. The a single-ended clock. The logic level is determined by internal buffer driving this pin may be disabled by ground- OVDD. Do not connect SCK–. In LVDS mode, drive SCK+ ing the REFINT pin. If the buffer is disabled, an external and SCK– with a differential clock. These pins must be reference may drive this pin in the range of 1.25V to 5V. differentially terminated by an external 100Ω resistor at the receiver (ADC).
VBYP1 (Pin 13):
Bypass this internally supplied pin to ground with a 1µF ceramic capacitor. The nominal output
OGND (Pin 23):
I/O Ground. This ground must be tied to voltage on this pin is 1.6V. the ground plane at a single point. OVDD is bypassed to this pin.
OVDD (Pin 14):
I/O Interface Digital Power. The range of OV
VBYP2 (Pin 24):
Bypass this internally supplied pin to DD is 1.71V to 2.5V. This supply is nominally set to the same supply as the host interface (CMOS: 1.8V or 2.5V, ground with a 1µF ceramic capacitor. The nominal output LVDS: 2.5V). Bypass OV voltage on this pin is 1.6V DD to OGND with a 0.1μF capacitor.
SDO1+, SDO1– (Pins 15, 16):
Channel 1 Serial Data Out-
CMOS/LVDS (Pin 25):
I/O Mode Select. Ground this pin put. The conversion result is shifted MSB first on each to enable CMOS mode, tie to OVDD to enable LVDS mode. falling edge of SCK. In CMOS mode, the result is output Float this pin to enable low power LVDS mode. on SDO1+. The logic level is determined by OVDD. Do not connect SDO1–. In LVDS mode, the result is output 232314fb 8 For more information www.linear.com/LTC2323-14 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Revision History Typical Application Related Parts
