Datasheet MCP606, MCP607, MCP608 (Microchip) - 3
| Manufacturer | Microchip |
| Description | The MCP606 operational amplifier (op amp) has a gain bandwidth product of 155 kHz with a low typical operating current of 18.7 µA and an offset voltage that is less than 250 µV |
| Pages / Page | 42 / 3 — MCP606/7/8/9. 1.0. ELECTRICAL. † Notice:. CHARACTERISTICS. Absolute … |
| File Format / Size | PDF / 707 Kb |
| Document Language | English |
MCP606/7/8/9. 1.0. ELECTRICAL. † Notice:. CHARACTERISTICS. Absolute Maximum Ratings †
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MCP606/7/8/9 1.0 ELECTRICAL † Notice:
Stresses above those listed under “Absolute
CHARACTERISTICS
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those
Absolute Maximum Ratings †
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended VDD – VSS ..7.0V periods may affect device reliability. Current at Input Pins ..±2 mA
††
See
Section 4.1.2 “Input Voltage and Current Limits”
. Analog Inputs (VIN+, VIN–) †† .. VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ... VSS – 0.3V to VDD + 0.3V Difference Input Voltage .. |VDD – VSS| Output Short Circuit Current .. Continuous Current at Output and Supply Pins ..±30 mA Storage Temperature ... –65° C to +150° C Maximum Junction Temperature (TJ).. .+150° C ESD Protection On All Pins (HBM; MM) .. ≥ 3 kV; 200V
DC CHARACTERISTICS Electrical Characteristics:
Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, V ≈ OUT VDD/2, VL = VDD/2, RL = 100 kΩ to VL, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions Input Offset
Input Offset Voltage V -250 — +250 µV OS Input Offset Drift with Temperature ΔVOS/ΔTA — ±1.8 — µV/°C TA = -40°C to +85°C Power Supply Rejection Ratio PSRR 80 93 — dB
Input Bias Current and Impedance
Input Bias Current IB — 1 — pA At Temperature IB — — 80 pA TA = +85°C Input Offset Bias Current IOS — 1 — pA Common Mode Input Impedance ZCM — 1013||6 — Ω||pF Differential Input Impedance ZDIFF — 1013||6 — Ω||pF
Common Mode
Common Mode Input Range VCMR VSS – 0.3 VDD – 1.1 V CMRR ≥ 75 dB Common Mode Rejection Ratio CMRR 75 91 — dB VDD = 5V, VCM = -0.3V to 3.9V
Open-Loop Gain
DC Open-Loop Gain AOL 105 121 — dB RL = 25 kΩ to VL, (Large-signal) VOUT = 50 mV to VDD – 50 mV DC Open-Loop Gain AOL 100 118 — dB RL = 5 kΩ to VL, (Large-signal) VOUT = 0.1V to VDD – 0.1V
Output
Maximum Output Voltage Swing VOL, VOH VSS + 15 — VDD – 20 mV RL = 25 kΩ to VL, 0.5V input overdrive VOL, VOH VSS + 45 — VDD – 60 mV RL = 5 kΩ to VL, 0.5V input overdrive Linear Output Voltage Range VOUT VSS + 50 — VDD – 50 mV RL = 25 kΩ to VL, AOL ≥ 105 dB VOUT VSS + 100 — VDD – 100 mV RL = 5 kΩ to VL, A ≥ OL 100 dB Output Short Circuit Current ISC — 7 — mA VDD = 2.5V ISC — 17 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 2.5 — 6.0 V Quiescent Current per Amplifier IQ — 18.7 25 µA IO = 0
Note 1:
All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 2.5V and 5.5V. © 2009 Microchip Technology Inc. DS11177F-page 3 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the CS Pin on the MCP608. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage at VDD = 5.5V. FIGURE 2-2: Input Offset Voltage at VDD = 2.5V. FIGURE 2-3: Quiescent Current vs. Power Supply Voltage. FIGURE 2-4: Input Offset Voltage Drift Magnitude at VDD = 5.5V. FIGURE 2-5: Input Offset Voltage Drift Magnitude at VDD = 2.5V. FIGURE 2-6: Quiescent Current vs. Ambient Temperature. FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature. FIGURE 2-8: Open-Loop Gain and Phase vs. Frequency. FIGURE 2-9: Channel-to-Channel Separation (MCP607 and MCP609 only). FIGURE 2-10: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-11: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-12: Input Noise Voltage Density vs. Frequency. FIGURE 2-13: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-14: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-15: CMRR, PSRR vs. Frequency. FIGURE 2-16: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-18: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-19: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-20: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-21: Slew Rate vs. Ambient Temperature. FIGURE 2-22: Output Voltage Headroom vs. Ambient Temperature at RL = 5 kW. FIGURE 2-23: The MCP606/7/8/9 Show No Phase Reversal. FIGURE 2-24: Output Short Circuit Current Magnitude vs. Ambient Temperature. FIGURE 2-25: Large-signal, Non-inverting Pulse Response. FIGURE 2-26: Small-signal, Non-inverting Pulse Response. FIGURE 2-27: Chip Select (CS) Hysteresis (MCP608 only). FIGURE 2-28: Large-signal, Inverting Pulse Response. FIGURE 2-29: Small-signal, Inverting Pulse Response. FIGURE 2-30: Amplifier Output Response Times vs. Chip Select (CS) Pulse (MCP608 only). FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Unity Gain Buffer has a Limited VOUT Range. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 MCP608 Chip Select 4.5 Supply Bypass 4.6 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.7 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.8 Application Circuits FIGURE 4-8: Low Side Battery Current Sensor. FIGURE 4-9: Photodiode (in Photo-voltaic mode) and Transimpedance Amplifier. FIGURE 4-10: Photodiode (in Photo- conductive mode) and Transimpedance Amplifier. FIGURE 4-11: Two Op Amp Instrumentation Amplifier. FIGURE 4-12: Three Op Amp Instrumentation Amplifier. FIGURE 4-13: Precision Gain with Good Load Isolation. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
MCP606/7/8/9 1.0 ELECTRICAL † Notice:
Stresses above those listed under “Absolute
CHARACTERISTICS
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those
Absolute Maximum Ratings †
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended VDD – VSS ..7.0V periods may affect device reliability. Current at Input Pins ..±2 mA
††
See
Section 4.1.2 “Input Voltage and Current Limits”
. Analog Inputs (VIN+, VIN–) †† .. VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ... VSS – 0.3V to VDD + 0.3V Difference Input Voltage .. |VDD – VSS| Output Short Circuit Current .. Continuous Current at Output and Supply Pins ..±30 mA Storage Temperature ... –65° C to +150° C Maximum Junction Temperature (TJ).. .+150° C ESD Protection On All Pins (HBM; MM) .. ≥ 3 kV; 200V
DC CHARACTERISTICS Electrical Characteristics:
Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, V ≈ OUT VDD/2, VL = VDD/2, RL = 100 kΩ to VL, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions Input Offset
Input Offset Voltage V -250 — +250 µV OS Input Offset Drift with Temperature ΔVOS/ΔTA — ±1.8 — µV/°C TA = -40°C to +85°C Power Supply Rejection Ratio PSRR 80 93 — dB
Input Bias Current and Impedance
Input Bias Current IB — 1 — pA At Temperature IB — — 80 pA TA = +85°C Input Offset Bias Current IOS — 1 — pA Common Mode Input Impedance ZCM — 1013||6 — Ω||pF Differential Input Impedance ZDIFF — 1013||6 — Ω||pF
Common Mode
Common Mode Input Range VCMR VSS – 0.3 VDD – 1.1 V CMRR ≥ 75 dB Common Mode Rejection Ratio CMRR 75 91 — dB VDD = 5V, VCM = -0.3V to 3.9V
Open-Loop Gain
DC Open-Loop Gain AOL 105 121 — dB RL = 25 kΩ to VL, (Large-signal) VOUT = 50 mV to VDD – 50 mV DC Open-Loop Gain AOL 100 118 — dB RL = 5 kΩ to VL, (Large-signal) VOUT = 0.1V to VDD – 0.1V
Output
Maximum Output Voltage Swing VOL, VOH VSS + 15 — VDD – 20 mV RL = 25 kΩ to VL, 0.5V input overdrive VOL, VOH VSS + 45 — VDD – 60 mV RL = 5 kΩ to VL, 0.5V input overdrive Linear Output Voltage Range VOUT VSS + 50 — VDD – 50 mV RL = 25 kΩ to VL, AOL ≥ 105 dB VOUT VSS + 100 — VDD – 100 mV RL = 5 kΩ to VL, A ≥ OL 100 dB Output Short Circuit Current ISC — 7 — mA VDD = 2.5V ISC — 17 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 2.5 — 6.0 V Quiescent Current per Amplifier IQ — 18.7 25 µA IO = 0
Note 1:
All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 2.5V and 5.5V. © 2009 Microchip Technology Inc. DS11177F-page 3 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the CS Pin on the MCP608. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage at VDD = 5.5V. FIGURE 2-2: Input Offset Voltage at VDD = 2.5V. FIGURE 2-3: Quiescent Current vs. Power Supply Voltage. FIGURE 2-4: Input Offset Voltage Drift Magnitude at VDD = 5.5V. FIGURE 2-5: Input Offset Voltage Drift Magnitude at VDD = 2.5V. FIGURE 2-6: Quiescent Current vs. Ambient Temperature. FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature. FIGURE 2-8: Open-Loop Gain and Phase vs. Frequency. FIGURE 2-9: Channel-to-Channel Separation (MCP607 and MCP609 only). FIGURE 2-10: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-11: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-12: Input Noise Voltage Density vs. Frequency. FIGURE 2-13: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-14: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-15: CMRR, PSRR vs. Frequency. FIGURE 2-16: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-18: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-19: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-20: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-21: Slew Rate vs. Ambient Temperature. FIGURE 2-22: Output Voltage Headroom vs. Ambient Temperature at RL = 5 kW. FIGURE 2-23: The MCP606/7/8/9 Show No Phase Reversal. FIGURE 2-24: Output Short Circuit Current Magnitude vs. Ambient Temperature. FIGURE 2-25: Large-signal, Non-inverting Pulse Response. FIGURE 2-26: Small-signal, Non-inverting Pulse Response. FIGURE 2-27: Chip Select (CS) Hysteresis (MCP608 only). FIGURE 2-28: Large-signal, Inverting Pulse Response. FIGURE 2-29: Small-signal, Inverting Pulse Response. FIGURE 2-30: Amplifier Output Response Times vs. Chip Select (CS) Pulse (MCP608 only). FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Unity Gain Buffer has a Limited VOUT Range. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 MCP608 Chip Select 4.5 Supply Bypass 4.6 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.7 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.8 Application Circuits FIGURE 4-8: Low Side Battery Current Sensor. FIGURE 4-9: Photodiode (in Photo-voltaic mode) and Transimpedance Amplifier. FIGURE 4-10: Photodiode (in Photo- conductive mode) and Transimpedance Amplifier. FIGURE 4-11: Two Op Amp Instrumentation Amplifier. FIGURE 4-12: Three Op Amp Instrumentation Amplifier. FIGURE 4-13: Precision Gain with Good Load Isolation. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
