Datasheet TC7650 (Microchip) - 5
| Manufacturer | Microchip |
| Description | TC7650 CMOS chopper-stabilized operational amplifier practically removes offset voltage error terms from system error calculations |
| Pages / Page | 14 / 5 — TC7650. 3.3. Intermodulation. FIGURE 3-1: |
| File Format / Size | PDF / 202 Kb |
| Document Language | English |
TC7650. 3.3. Intermodulation. FIGURE 3-1:
Model Line for this Datasheet
Text Version of Document
TC7650
tion region, where the main amplifier takes over from ing sum and difference frequencies, and causing dis- the null amplifier. The clock frequency sets the transi- turbances to the gain and phase versus frequency tion region. characteristics near the chopping frequency. These effects are substantially reduced in the TC7650 by
3.3 Intermodulation
feeding the nulling circuit with a dynamic current corre- sponding to the compensation capacitor current in such Previous chopper stabilized amplifiers have suffered a way as to cancel that portion of the input signal due from intermodulation effects between the chopper fre- to a finite AC gain. The intermodulation and gain/phase quency and input signals. These arise because the disturbances are held to very low values, and can gen- finite AC gain of the amplifier results in a small AC sig- erally be ignored. nal at the input. This is seen by the zeroing circuit as an error signal, which is chopped and fed back, thus inject-
FIGURE 3-1: TC7650 CONTAINS A NULLING AND MAIN AMPLIFIER. OFFSET CORRECTION VOLTAGES ARE STORED ON TWO EXTERNAL CAPACITORS.
Main V+ + Amplifier Analog Input Null VOUT - V- Gain = AM B
TC7650
+ B CB Null A A - Null CA Amplifier Gain = AN , Offset = VOSN
FIGURE 3-2: NULLING CAPACITOR 3.5 Clock Operation CONNECTION
The internal oscillator is set for a 200Hz nominal chop- V V V DD SS DD ping frequency on both the 8- and 14-pin DIPs. With the 14-pin DIP TC7650, the 200 Hz internal chopping fre- 4 11 2 7 quency is available at the internal clock output (Pin 12). - - 7 A 400Hz nominal signal will be present at the external 10 6
TC7650 TC7650
clock input pin (Pin 13) with INT/EXT high or open. This 5 1 3 4 is the internal clock signal before a divide-by-two oper- + + 8 CB ation. 8 V 2 SS 1 The 14-pin DIP device can be driven by an external clock. The INT/EXT input (Pin 14) has an internal pull- CA CB CA up and may be left open for internal clock operation. If an external clock is used, INT/EXT must be tied to VSS 14-PIN PACKAGE 8-PIN PACKAGE (Pin 7) to disable the internal clock. The external clock signal is applied to the external clock input (Pin 13).
3.4 Nulling Capacitor Connection
The external clock amplitude should swing between The offset voltage correction capacitors are connected VDD and ground for power supplies up to ±6V and to C between V+ and V+ -6V for higher supply voltages. A and CB. The common capacitor connection is made to VSS (Pin 4) on the 8-pin packages and to At low frequencies the external clock duty cycle is not capacitor return (CRETN, Pin 8) on the 14-pin packages. critical, since an internal divide-by-two gives the The common connection should be made through a desired 50% switching duty cycle. The offset storage separate PC trace or wire to avoid voltage drops. The correction capacitors are charged only when the exter- capacitors outside foil, if possible, should be connected nal clock input is high. A 50% to 80% external clock to CRETN or VSS. 2001-2012 Microchip Technology Inc. DS21463C-page 5
tion region, where the main amplifier takes over from ing sum and difference frequencies, and causing dis- the null amplifier. The clock frequency sets the transi- turbances to the gain and phase versus frequency tion region. characteristics near the chopping frequency. These effects are substantially reduced in the TC7650 by
3.3 Intermodulation
feeding the nulling circuit with a dynamic current corre- sponding to the compensation capacitor current in such Previous chopper stabilized amplifiers have suffered a way as to cancel that portion of the input signal due from intermodulation effects between the chopper fre- to a finite AC gain. The intermodulation and gain/phase quency and input signals. These arise because the disturbances are held to very low values, and can gen- finite AC gain of the amplifier results in a small AC sig- erally be ignored. nal at the input. This is seen by the zeroing circuit as an error signal, which is chopped and fed back, thus inject-
FIGURE 3-1: TC7650 CONTAINS A NULLING AND MAIN AMPLIFIER. OFFSET CORRECTION VOLTAGES ARE STORED ON TWO EXTERNAL CAPACITORS.
Main V+ + Amplifier Analog Input Null VOUT - V- Gain = AM B
TC7650
+ B CB Null A A - Null CA Amplifier Gain = AN , Offset = VOSN
FIGURE 3-2: NULLING CAPACITOR 3.5 Clock Operation CONNECTION
The internal oscillator is set for a 200Hz nominal chop- V V V DD SS DD ping frequency on both the 8- and 14-pin DIPs. With the 14-pin DIP TC7650, the 200 Hz internal chopping fre- 4 11 2 7 quency is available at the internal clock output (Pin 12). - - 7 A 400Hz nominal signal will be present at the external 10 6
TC7650 TC7650
clock input pin (Pin 13) with INT/EXT high or open. This 5 1 3 4 is the internal clock signal before a divide-by-two oper- + + 8 CB ation. 8 V 2 SS 1 The 14-pin DIP device can be driven by an external clock. The INT/EXT input (Pin 14) has an internal pull- CA CB CA up and may be left open for internal clock operation. If an external clock is used, INT/EXT must be tied to VSS 14-PIN PACKAGE 8-PIN PACKAGE (Pin 7) to disable the internal clock. The external clock signal is applied to the external clock input (Pin 13).
3.4 Nulling Capacitor Connection
The external clock amplitude should swing between The offset voltage correction capacitors are connected VDD and ground for power supplies up to ±6V and to C between V+ and V+ -6V for higher supply voltages. A and CB. The common capacitor connection is made to VSS (Pin 4) on the 8-pin packages and to At low frequencies the external clock duty cycle is not capacitor return (CRETN, Pin 8) on the 14-pin packages. critical, since an internal divide-by-two gives the The common connection should be made through a desired 50% switching duty cycle. The offset storage separate PC trace or wire to avoid voltage drops. The correction capacitors are charged only when the exter- capacitors outside foil, if possible, should be connected nal clock input is high. A 50% to 80% external clock to CRETN or VSS. 2001-2012 Microchip Technology Inc. DS21463C-page 5
