Datasheet TC7650 (Microchip) - 6

TC7650
positive duty cycle is desired for frequencies above
FIGURE 3-5: INVERTING AMPLIFIER WITH
500Hz to ensure transients settle before the internal
OPTIONAL CLAMP
switches open. R2 The external clock input can also be used as a strobe input. If a strobe signal is connected at the external Clamp R clock input so that it is LOW during the time an overload 1 signal is applied, neither capacitor will be charged. The Input leakage currents at the capacitors pins are very low. At
TC7650
C Output * 25°C a typical TC7650 will drift less than 10V/sec. + R C (R1 R2) ‡ 100 kΩ
3.6 Output Clamp
For Full Clamp Effect Chopper-stabilized systems can show long recovery *Connect To V– R 0.1 F µ 0.1 F µ times from overloads. If the output is driven to either On 8-Pin DIP. supply rail, output saturation occurs. The inputs are no longer held at a "virtual ground." The V The output clamp circuit is shown in Figure 3-3, with OS null circuit treats the differential signal as an offset and tries to cor- typical inverting and non-inverting circuit connections rect it by charging the external capacitors. The nulling shown in Figures 3-4 and 3-5. Output voltage versus circuit also saturates. Once the input signal returns to clamp circuit current characteristics are shown in the normal, the response time is lengthened by the long typical operating curves. For the clamp to be fully effec- recovery time of the nulling amplifier and external tive, the impedance across the clamp output should be capacitors. greater than 100k. Through an external clamp connection, the TC7650
3.7 Latch-Up Avoidance
eliminates the overload recovery problem by reducing the feedback network gain before the output voltage Junction-isolated CMOS circuits inherently include a reaches either supply rail. parasitic 4-layer (p-n-p-n) structure which has charac-
FIGURE 3-3: INTERNAL CLAMP CIRCUIT
teristics similar to an SCR. Under certain circum- stances this junction may be triggered into a low- Internal impedance state, resulting in excessive supply current. Positive Clamp Bias ≈ V+ - VT ≈ V+ - 0.7 To avoid this condition, no voltage greater than 0.3V P-Channel beyond the supply rails should be applied to any pin. In general, the amplifier supplies must be established Output either at the same time or before any input signals are Clamp Pin applied. If this is not possible, the drive circuits must N-Channel limit input current flow to under 0.1mA to avoid latch- up.
3.8 Thermoelectric Potentials FIGURE 3-4: NON-INVERTING AMPLIFIER WITH OPTIONAL CLAMP
Precision DC measurements are ultimately limited by *Connect To V 0.1µF thermoelectric potentials developed in thermocouple SS On 8-Pin DIP. junctions of dissimilar metals, alloys, silicon, etc. Unless all junctions are at the same temperature, ther- C * moelectric voltages, typically around 0.1V/°C, but up + Input R to tens of V/°C for some materials, will be generated.
TC7650
C Output In order to realize the benefits extremely-low offset volt- R2 ages provide, it is essential to take special precautions Clamp to avoid temperature gradients. All components should be enclosed to eliminate air movement, especially R3 R those caused by power dissipating elements in the sys- 1 R3 + (R1/R2) ‡ 100 kΩ tem. Low thermoelectric co-efficient connections For Full Clamp Effect should be used where possible and power supply volt- ages and power dissipation should be kept to a mini- mum. High impedance loads are preferable, and separation from surrounding heat dissipating elements is advised. DS21463C-page 6  2001-2012 Microchip Technology Inc.