Datasheet MCP3202 (Microchip) - 2

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MCP3202 1.0 ELECTRICAL † Notice:
Stresses above those listed under “Absolute
CHARACTERISTICS
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those
Absolute Maximum Ratings †
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended VDD - VSS ...7.0V periods may affect device reliability. All Inputs and Outputs w.r.t. VSS ... -0.6V to VDD + 0.6V Storage Temperature...-65°C to +150°C Ambient temperature with power applied...-65°C to +150°C Maximum Junction Temperature (TJ)..+150°C ESD Protection On All Pins (HBM)  4 kV
ELECTRICAL CHARACTERISTICS Electrical Characteristics:
Unless otherwise noted, all parameters apply at VDD = 5.5V, VSS = 0V, TA = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE.
Parameter Sym Min. Typ. Max. Units Conditions Conversion Rate:
Conversion Time tCONV — — 12 clock cycles Analog Input Sample Time tSAMPLE 1.5 clock cycles Throughput Rate fSAMPL — — 100 ksps VDD = VREF = 5V — — 50 ksps VDD = VREF = 2.7V
DC Accuracy:
Resolution 12 bits Integral Nonlinearity INL — ±0.75 ±1 LSB MCP3202-B — ±1 ±2 LSB MCP3202-C Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes over temperature Offset Error — ±1.25 ±3 LSB Gain Error — ±1.25 ±5 LSB
Dynamic Performance:
Total Harmonic Distortion THD — -82 — dB VIN = 0.1V to 4.9V@1 kHz Signal-to-Noise and Distortion SINAD — 72 — dB VIN = 0.1V to 4.9V@1 kHz (SINAD) Spurious Free Dynamic Range SFDR — 86 — dB VIN = 0.1V to 4.9V@1 kHz
Analog Inputs:
Input Voltage Range for CH0 or VSS — VDD V CH1 in Single-Ended Mode Input Voltage Range for IN+ in IN+ IN- — VDD+IN- See Sections 3.1 and 4.1 Pseudo-Differential Mode Input Voltage Range for IN- in IN- VSS-100 — VSS+100 mV See Sections 3.1 and 4.1 Pseudo-Differential Mode Leakage Current — .001 ±1 A Switch Resistance RSS — 1 k — Ω See Figure 4-1 Sample Capacitor CSAMPLE — 20 — pF See Figure 4-1
Digital Input/Output:
Data Coding Format Straight Binary High Level Input Voltage VIH 0.7 VDD — — V Low Level Input Voltage VIL — — 0.3 VDD V
Note 1:
This parameter is established by characterization and not 100% tested.
2:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See
Section 6.2 “Maintaining Minimum Clock Speed”
for more information. DS21034F-page 2  1999-2011 Microchip Technology Inc. Document Outline MCP3202 - 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface Functional Block Diagram Package Types 1.0 Electrical Characteristics Absolute Maximum Ratings † FIGURE 1-1: Serial Timing. FIGURE 1-2: Test Circuits. 2.0 Typical Performance Characteristics FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate. FIGURE 2-2: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). FIGURE 2-5: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). FIGURE 2-7: Integral Nonlinearity (INL) vs. Temperature. FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate. FIGURE 2-9: Differential Nonlinearity (DNL) vs. VDD. FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V). FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V). FIGURE 2-12: Differential Nonlinearity (DNL) vs. VDD. FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part). FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature. FIGURE 2-15: Gain Error vs. VDD. FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V). FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V). FIGURE 2-18: Offset Error vs. VDD. FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-20: Signal-to-Noise Ratio (SNR) vs. Input Frequency. FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency. FIGURE 2-22: Offset Error vs. Temperature. FIGURE 2-23: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency. FIGURE 2-24: Signal-to-Noise and Distortion (SINAD) vs. Signal Level. FIGURE 2-25: Effective Number of Bits (ENOB) vs. VDD. FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. FIGURE 2-27: Frequency Spectrum of 10 kHz input (Representative Part). FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency. FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency. FIGURE 2-30: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V). FIGURE 2-31: IDD vs. VDD. FIGURE 2-32: IDD vs. Clock Frequency. FIGURE 2-33: IDD vs. Temperature. FIGURE 2-34: IDDS vs. VDD. FIGURE 2-35: IDDS vs. Temperature. FIGURE 2-36: Analog Input leakage current vs. Temperature. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Inputs (CH0/CH1) 3.2 Chip Select/Shutdown (CS/SHDN) 3.3 Serial Clock (CLK) 3.4 Serial Data Input (DIN) 3.5 Serial Data Output (DOUT) 4.0 Device Operation 4.1 Analog Inputs 4.2 Digital Output Code EQUATION 4-1: FIGURE 4-1: Analog Input Model. FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. 5.0 Serial Communications 5.1 Overview TABLE 5-1: Configuration Bits for the MCP3202 FIGURE 5-1: Communication with the MCP3202 using MSB first format only. FIGURE 5-2: Communication with MCP3202 using LSB first format. 6.0 Applications Information 6.1 Using the MCP3202 with Microcontroller (MCU) SPI Ports FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). 6.2 Maintaining Minimum Clock Speed 6.3 Buffering/Filtering the Analog Inputs FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti- aliasing filter for the signal being converted by the MCP3202. 6.4 Layout Considerations FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. 7.0 Packaging Information 7.1 Package Marking Information Appendix A: Revision History Worldwide Sales and Service