Datasheet LTC4310-1, LTC4310-2 (Analog Devices) - 8

LTC4310-1/LTC4310-2
operaTion (LTC4310 refers to both LTC4310-1 and LTC4310-2)
The LTC4310 provides fully bidirectional communications bus rise rate to dV/dtRISE via the rise rate limiter circuitry. between two I2C or SMBus buses whose grounds are It also transmits a high to the other LTC4310. If the SDA isolated from one another. Clock stretching, clock syn- rise rate falls below the threshold, it is assumed that an- chronization, arbitration and data acknowledging all work other pull-down on the bus has turned on and is pulling seamlessly across the barrier, regardless of the locations SDA low, and a command to pull the far side low is sent of the master(s) and slave(s). across the isolation barrier. Referring to the application circuit shown in Figure 1, an When SDA rises above 0.35 • VCC, the rise rate limiter LTC4310 is located on each side of the isolation barrier. circuitry is deactivated. When SDA rises above 0.45 • VCC, Each LTC4310 contains logic detection circuitry that can the rise time accelerator current IBOOST is activated, which differentiate externally driven SDA and SCL logic signals provides a strong, slew-limited pull-up current to reduce from its own output signals. Each LTC4310 converts the system rise time. logic state of the externally driven signals into a sequence The LTC4310 contains power-on reset (POR) circuitry that of pulses that are then transmitted across the isolation bar- sets the data and clock pins in a high impedance state and rier via an Ethernet transformer (or coupling capacitors for deactivates the transmit and receive circuitry until the EN low isolation voltage applications) to the other LTC4310. voltage is high, the device is not in thermal shutdown Each LTC4310 also receives and decodes corresponding and the V pulses from the other LTC4310 and drives its SDA and CC voltage is above the 2.4V UVLO threshold voltage. The LTC4310 enters thermal shutdown when the SCL pins accordingly. die temperature exceeds 150°C. Grounding EN sets the Transmissions occur on the TXP and TXN pins in a sequence LTC4310 in a near-zero current mode. of 1.25V pulses. The LTC4310 receives messages on its After the LTC4310 exits POR, STOP bit and bus idle detector RXP and RXN pins. Signals having less than 500mV dif- circuitry monitors the logic state of its own SDA and SCL ferential voltages are rejected to provide noise immunity bus and of the other I2C bus in the system via RXP and against common-mode transients. RXN. When a STOP bit or bus idle occurs simultaneously When the LTC4310 receives a message to drive SDA low, on both I2C buses, the LTC4310 activates its SDA and SCL it regulates SDA to 0.35V. If an external device pulls SDA drivers, logic detection circuitry and rise time accelerators below 0.35V during this time, the LTC4310 detects this and drives READY low. condition and immediately transmits a LOW to the other The stuck bus timer and recovery circuitry disable the LTC4310. SDA and SCL driver, logic detection circuitry and rise When an external pull-down device drives SDA below time accelerators if the bus is low for 37ms. A stuck bus 0.45 • VCC from a logic high, TXP and TXN transmit a also causes READY to be released high. If the stuck bus message across the isolation barrier instructing the other releases high, the I2C driver and accelerator circuitry are LTC4310 to drive its SDA line low. reactivated when a STOP bit or bus idle occurs simultane- When the external pull-down device turns off and SDA is ously on both I2C buses, as previously described. rising between 0V and 0.35 • VCC, the LTC4310 limits the 431012fa 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts