Datasheet LTC4300A-3 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Level Shifting Hot Swappable 2-Wire Bus Buffer with Enable |
| Pages / Page | 14 / 8 — Figure 1. Input–Output Connection Low to High Transition. Figure 2. … |
| File Format / Size | PDF / 216 Kb |
| Document Language | English |
Figure 1. Input–Output Connection Low to High Transition. Figure 2. Input–Output Connection High to Low Transition
Model Line for this Datasheet
- LTC4300A-3CDD#PBF LTC4300A-3CDD#PBF LTC4300A-3CDD#TRPBF LTC4300A-3CDD#TRPBF LTC4300A-3CMS8#PBF LTC4300A-3CMS8#PBF LTC4300A-3CMS8#TRPBF LTC4300A-3CMS8#TRPBF LTC4300A-3IDD#PBF LTC4300A-3IDD#PBF LTC4300A-3IDD#TRPBF LTC4300A-3IDD#TRPBF LTC4300A-3IMS8#PBF LTC4300A-3IMS8#PBF LTC4300A-3IMS8#TRPBF LTC4300A-3IMS8#TRPBF
Text Version of Document
LTC4300A-3 OUTPUT INPUT INPUT OUTPUT SIDE SIDE SIDE SIDE 50pF 150pF 150pF 50pF 0.5V/DIV 0.5V/DIV 4300a3 F01 4300a3 F02 200ns/DIV 200ns/DIV
Figure 1. Input–Output Connection Low to High Transition Figure 2. Input–Output Connection High to Low Transition
supply voltage, temperature and the pull-up resistors and For example, assume an SMBus system with VCC = 3V, equivalent bus capacitances on both sides of the bus. The a 10k pull-up resistor and equivalent bus capacitance of Typical Performance Characteristics section shows tPHL 200pF. The rise time of an SMBus system is calculated as a function of temperature and voltage for 10k pull-up from (VIL(MAX) – 0.15V) to (VIH(MIN) + 0.15V), or 0.65V resistors and 100pF equivalent capacitance on both sides to 2.25V. It takes an RC circuit 0.92 time constants to of the part. By comparison with Figure 2, the VCC = VCC2 traverse this voltage for a 3V supply; in this case, 0.92 = 3.3V curve shows that increasing the capacitance from • (10k • 200pF) = 1.84µs. Thus, the system exceeds the 50pF to 100pF results in a propagation delay increase maximum allowed rise time of 1µs by 84%. However, from 55ns to 75ns. Larger output capacitances translate using the rise time accelerators, which are activated at a to longer delays (up to 150ns). Users must quantify the DC threshold of below 0.65V, the worst-case rise time is: difference in propagation times for a rising edge versus (2.25V – 0.65V) • 200pF/1mA = 320ns, which meets the a falling edge in their systems and adjust setup and hold 1µs rise time requirement. times accordingly.
ENABLE Low Current Disable Rise Time Accelerators
Grounding the ENABLE pin disconnects the backplane side Once connection has been established, rise time accelerator from the card side, disables the rise time accelerators, circuits on all four SDA and SCL pins are activated. These disables the bus precharge circuitry and puts the part in a allow the user to choose weaker DC pull-up currents on near-zero current state. When the pin voltage is driven all the bus, reducing power consumption while still meet- the way to VCC, the part waits for data transactions on both ing system rise time requirements. During positive bus the backplane and card sides to be complete (as described transitions, the LTC4300A-3 switches in 2mA (typical) of in the Start-Up section) before reconnecting the two sides. current to quickly slew the SDA and SCL lines once their DC voltages exceed 0.6V. Using a general rule of 20pF of capacitance for every device on the bus (10pF for the device and 10pF for interconnect), choose a pull-up current so that the bus will rise on its own at a rate of at least 1.25V/µs to guarantee activation of the accelerators. 4300a3fa 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts Typical Application
Figure 1. Input–Output Connection Low to High Transition Figure 2. Input–Output Connection High to Low Transition
supply voltage, temperature and the pull-up resistors and For example, assume an SMBus system with VCC = 3V, equivalent bus capacitances on both sides of the bus. The a 10k pull-up resistor and equivalent bus capacitance of Typical Performance Characteristics section shows tPHL 200pF. The rise time of an SMBus system is calculated as a function of temperature and voltage for 10k pull-up from (VIL(MAX) – 0.15V) to (VIH(MIN) + 0.15V), or 0.65V resistors and 100pF equivalent capacitance on both sides to 2.25V. It takes an RC circuit 0.92 time constants to of the part. By comparison with Figure 2, the VCC = VCC2 traverse this voltage for a 3V supply; in this case, 0.92 = 3.3V curve shows that increasing the capacitance from • (10k • 200pF) = 1.84µs. Thus, the system exceeds the 50pF to 100pF results in a propagation delay increase maximum allowed rise time of 1µs by 84%. However, from 55ns to 75ns. Larger output capacitances translate using the rise time accelerators, which are activated at a to longer delays (up to 150ns). Users must quantify the DC threshold of below 0.65V, the worst-case rise time is: difference in propagation times for a rising edge versus (2.25V – 0.65V) • 200pF/1mA = 320ns, which meets the a falling edge in their systems and adjust setup and hold 1µs rise time requirement. times accordingly.
ENABLE Low Current Disable Rise Time Accelerators
Grounding the ENABLE pin disconnects the backplane side Once connection has been established, rise time accelerator from the card side, disables the rise time accelerators, circuits on all four SDA and SCL pins are activated. These disables the bus precharge circuitry and puts the part in a allow the user to choose weaker DC pull-up currents on near-zero current state. When the pin voltage is driven all the bus, reducing power consumption while still meet- the way to VCC, the part waits for data transactions on both ing system rise time requirements. During positive bus the backplane and card sides to be complete (as described transitions, the LTC4300A-3 switches in 2mA (typical) of in the Start-Up section) before reconnecting the two sides. current to quickly slew the SDA and SCL lines once their DC voltages exceed 0.6V. Using a general rule of 20pF of capacitance for every device on the bus (10pF for the device and 10pF for interconnect), choose a pull-up current so that the bus will rise on its own at a rate of at least 1.25V/µs to guarantee activation of the accelerators. 4300a3fa 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts Typical Application
