Datasheet LTC4316 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Single I2C/SMBus Address Translator |
| Pages / Page | 16 / 8 — OPERATION Table 1. DESCRIPTION. BINARY ADDRESS. 7-BIT HEX ADDRESS. 8-BIT … |
| File Format / Size | PDF / 212 Kb |
| Document Language | English |
OPERATION Table 1. DESCRIPTION. BINARY ADDRESS. 7-BIT HEX ADDRESS. 8-BIT HEX ADDRESS. WITHOUT R/W. WITH R/W=0. R/W
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Text Version of Document
LTC4316
OPERATION Table 1. DESCRIPTION BINARY ADDRESS 7-BIT HEX ADDRESS 8-BIT HEX ADDRESS WITHOUT R/W WITH R/W=0 a6 a5 a4 a3 a2 a1 a0 R/W
Input Address from SDAIN 0 0 1 1 0 1 0 0 0x1A 0x34 Translation Byte 0 0 0 0 0 0 1 0 0x01 0x02 Output Address to SDAOUT 0 0 1 1 0 1 1 0 0x1B 0x36
System Configurations Setting the Translation Byte
There are several ways that individual slaves or banks of When the LTC4316 is first powered up or any time a rising slaves can be connected to an LTC4316. In Figure 3, each edge is detected on the ENABLE pin, the LTC4316 reads slave is paired with an LTC4316. This configuration allows the voltages at XORH and XORL pins to determine the for maximum flexibility in allocating the bus addresses. 7-bit translation byte. These voltages are referenced to Both read and write operations and all protocols supported VCC so a resistive divider at each of these pins is the most by the LTC4316 are allowed. Figure 4 shows two slaves convenient way to set the voltages. The required transla- with different hardwired addresses translated to two dif- tion byte can be determined by taking the bitwise XOR of ferent addresses using a single LTC4316 and a common the slave’s original address and the desired input address. translation byte. A program is available to help the user The voltages at the XORH and XORL pins configure the visualize an I2C bus with the LTC4316; this program can translation byte. The XORL voltage configures the lower be found in the following link: 4 translation bits (excluding the R/W bit), while the XORH voltage configures the upper 3 translation bits. Tables 2 www.linear.com/TranslatorTool and 3 show the recommended resistive divider values. RLT and RLB are the top and bottom resistors connected to XORL, while RHT and RHB are the top and bottom resistors SCLIN SCLOUT SCL connected to XORH (Figure 5). Use 1% tolerance resistors 00110010 LTC4316 SLAVE for R 00000110 LT, RLB, RHT and RHB. #1 #1 00110100 SDAIN SDAOUT SDA SLAVE #1 HARDWIRED ADDRESS INPUT ADDRESS 0x32 0x34 SCL TRANSLATION BYTE 0x06 SLAVE #2 SDA SCLIN SCLOUT SCL HARDWIRED ADDRESS 00110110 LTC4316 SLAVE 0x34 00000010 SCL #2 #3 00110100 SDAIN SDAOUT SDA MASTER SCLIN SCLOUT SCL 00110110 SLAVE SLAVE #3 HARDWIRED ADDRESS SDA LTC4316 00000010 #1 00110100 INPUT ADDRESS 0x36 0x34 SDAIN SDAOUT SDA SCL TRANSLATION BYTE 0x02 TRANSLATION BYTE HARDWIRED ADDRESS MASTER 0x02 0x34 SDA SCL SLAVE #1 SCL INPUT ADDRESS 00110010 SLAVE 0x36 SLAVE 00000010 #2 #3 SLAVE #3 00110000 SDA INPUT ADDRESS SDA 0x32 HARDWIRED ADDRESS HARDWIRED ADDRESS 0x34 0x30 4316 F03 4316 F04
Figure 3. Two Independent Address Translation Figure 4. Two Slaves Sharing One LTC4316
4316fa 8 For more information www.linear.com/LTC4316
OPERATION Table 1. DESCRIPTION BINARY ADDRESS 7-BIT HEX ADDRESS 8-BIT HEX ADDRESS WITHOUT R/W WITH R/W=0 a6 a5 a4 a3 a2 a1 a0 R/W
Input Address from SDAIN 0 0 1 1 0 1 0 0 0x1A 0x34 Translation Byte 0 0 0 0 0 0 1 0 0x01 0x02 Output Address to SDAOUT 0 0 1 1 0 1 1 0 0x1B 0x36
System Configurations Setting the Translation Byte
There are several ways that individual slaves or banks of When the LTC4316 is first powered up or any time a rising slaves can be connected to an LTC4316. In Figure 3, each edge is detected on the ENABLE pin, the LTC4316 reads slave is paired with an LTC4316. This configuration allows the voltages at XORH and XORL pins to determine the for maximum flexibility in allocating the bus addresses. 7-bit translation byte. These voltages are referenced to Both read and write operations and all protocols supported VCC so a resistive divider at each of these pins is the most by the LTC4316 are allowed. Figure 4 shows two slaves convenient way to set the voltages. The required transla- with different hardwired addresses translated to two dif- tion byte can be determined by taking the bitwise XOR of ferent addresses using a single LTC4316 and a common the slave’s original address and the desired input address. translation byte. A program is available to help the user The voltages at the XORH and XORL pins configure the visualize an I2C bus with the LTC4316; this program can translation byte. The XORL voltage configures the lower be found in the following link: 4 translation bits (excluding the R/W bit), while the XORH voltage configures the upper 3 translation bits. Tables 2 www.linear.com/TranslatorTool and 3 show the recommended resistive divider values. RLT and RLB are the top and bottom resistors connected to XORL, while RHT and RHB are the top and bottom resistors SCLIN SCLOUT SCL connected to XORH (Figure 5). Use 1% tolerance resistors 00110010 LTC4316 SLAVE for R 00000110 LT, RLB, RHT and RHB. #1 #1 00110100 SDAIN SDAOUT SDA SLAVE #1 HARDWIRED ADDRESS INPUT ADDRESS 0x32 0x34 SCL TRANSLATION BYTE 0x06 SLAVE #2 SDA SCLIN SCLOUT SCL HARDWIRED ADDRESS 00110110 LTC4316 SLAVE 0x34 00000010 SCL #2 #3 00110100 SDAIN SDAOUT SDA MASTER SCLIN SCLOUT SCL 00110110 SLAVE SLAVE #3 HARDWIRED ADDRESS SDA LTC4316 00000010 #1 00110100 INPUT ADDRESS 0x36 0x34 SDAIN SDAOUT SDA SCL TRANSLATION BYTE 0x02 TRANSLATION BYTE HARDWIRED ADDRESS MASTER 0x02 0x34 SDA SCL SLAVE #1 SCL INPUT ADDRESS 00110010 SLAVE 0x36 SLAVE 00000010 #2 #3 SLAVE #3 00110000 SDA INPUT ADDRESS SDA 0x32 HARDWIRED ADDRESS HARDWIRED ADDRESS 0x34 0x30 4316 F03 4316 F04
Figure 3. Two Independent Address Translation Figure 4. Two Slaves Sharing One LTC4316
4316fa 8 For more information www.linear.com/LTC4316
