Datasheet LTC4316 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Single I2C/SMBus Address Translator |
| Pages / Page | 16 / 10 — OPERATION. Precharge and Hot Swap. Figure 7. Extra Transitions on SDAOUT … |
| File Format / Size | PDF / 212 Kb |
| Document Language | English |
OPERATION. Precharge and Hot Swap. Figure 7. Extra Transitions on SDAOUT While SCL Is Low. Pass-Through Mode
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LTC4316
OPERATION
N1, N2 and N3 are off, the READY pin is pulled low and ADDRESS BITS the quiescent current drops to 350μA. SCLIN
Precharge and Hot Swap
SDAIN 0 1 0 1 When the LTC4316 is first powered on, switches N1 and TRANSLATION BYTE 0 1 1 0 N2 are initially off. This allows a LTC4316 and its con- nected slaves to be hot swapped onto an active I2C bus. SDAOUT 0 0 1 1 Internal precharge circuitry initially sets the bus lines to GLITCH GLITCH 1V through a 200k resistor, minimizing disturbance to an N2 GATE N2 OFF 4316 F07 active bus when the LTC4316 is connected. The LTC4316
Figure 7. Extra Transitions on SDAOUT While SCL Is Low
keeps N1 and N2 off until ENABLE goes high, the XORL/ XORH pins are read, and both sides of the I2C bus are pins to match the supply voltage at each side. VCC must idle (indicated either by a STOP bit or all bus pins high for be powered from the lower of the two supply voltages longer than 120μs). Once these conditions are met, N1 for level shifting to operate correctly. For example, if the and N2 turn on, and the READY pin goes high to indicate input bus is powered by a 5V supply and the output bus that the LTC4316 is ready to start address translation. is powered by a 3.3V supply, the LTC4316 VCC pin must be connected to the 3.3V supply as shown in Figure 8.
Pass-Through Mode
If the master wants to communicate with the slave us- 5V 3.3V ing the general call address, it can temporarily disable VCC address translation by pulling XORH high. This disables SCLIN SCLOUT address translation and keeps N1 and N2 on regardless SLAVE MASTER LTC4316 of the activity on the buses. Any translation that may be in #1 progress is stopped immediately when XORH goes high. SDAIN SDAOUT 4316 F08
Extra Transitions on SDAOUT Figure 8. A 5V to 3.3V Level Translation Application
In an I2C /SMBus system, the master changes the state of If the LTC4316 supply pin is connected to the higher bus the SDA line when SCL is low. The LTC4316 also advances supply, current may flow through the switches N1 and the address translation byte shift register when the SCLIN N2 to the bus with lower supply. If the voltage difference is low. The translation byte transitions occur approximately is less than 1V, this current is limited to less than 10μA. 100ns after the falling edge of SCLIN. If the SDAIN tran- This allows the input and output buses to be connected sitions sent by the master do not coincide exactly with to nominally identical supplies that may have up ±10% the LTC4316 address translation bit transitions, an extra tolerance, and the LTC4316 V transition on SDAOUT may appear (Figure 7). These extra CC pin can be connected to either supply. SDA transitions are like glitches similar to those occurring during normal Acknowledge bit transitions and do not pose
Extra START and STOP Bits
problems in the system because devices on the bus latch SDA data only when SCL is high. During normal operation, an I2C master should not issue a START or STOP bit within a data byte. I2C slave behavior
Level Translation and Supply Voltage Matching
when such a command is received can be unpredictable. The LTC4316 will recover automatically when an unex- The LTC4316 can operate with different supply voltages pected START or STOP is received during the address byte; on the input and output bus, and it will level shift the however, depending on the state of the translating bits, voltages on the SCLIN, SDAIN, SCLOUT, and SDAOUT 4316fa 10 For more information www.linear.com/LTC4316
OPERATION
N1, N2 and N3 are off, the READY pin is pulled low and ADDRESS BITS the quiescent current drops to 350μA. SCLIN
Precharge and Hot Swap
SDAIN 0 1 0 1 When the LTC4316 is first powered on, switches N1 and TRANSLATION BYTE 0 1 1 0 N2 are initially off. This allows a LTC4316 and its con- nected slaves to be hot swapped onto an active I2C bus. SDAOUT 0 0 1 1 Internal precharge circuitry initially sets the bus lines to GLITCH GLITCH 1V through a 200k resistor, minimizing disturbance to an N2 GATE N2 OFF 4316 F07 active bus when the LTC4316 is connected. The LTC4316
Figure 7. Extra Transitions on SDAOUT While SCL Is Low
keeps N1 and N2 off until ENABLE goes high, the XORL/ XORH pins are read, and both sides of the I2C bus are pins to match the supply voltage at each side. VCC must idle (indicated either by a STOP bit or all bus pins high for be powered from the lower of the two supply voltages longer than 120μs). Once these conditions are met, N1 for level shifting to operate correctly. For example, if the and N2 turn on, and the READY pin goes high to indicate input bus is powered by a 5V supply and the output bus that the LTC4316 is ready to start address translation. is powered by a 3.3V supply, the LTC4316 VCC pin must be connected to the 3.3V supply as shown in Figure 8.
Pass-Through Mode
If the master wants to communicate with the slave us- 5V 3.3V ing the general call address, it can temporarily disable VCC address translation by pulling XORH high. This disables SCLIN SCLOUT address translation and keeps N1 and N2 on regardless SLAVE MASTER LTC4316 of the activity on the buses. Any translation that may be in #1 progress is stopped immediately when XORH goes high. SDAIN SDAOUT 4316 F08
Extra Transitions on SDAOUT Figure 8. A 5V to 3.3V Level Translation Application
In an I2C /SMBus system, the master changes the state of If the LTC4316 supply pin is connected to the higher bus the SDA line when SCL is low. The LTC4316 also advances supply, current may flow through the switches N1 and the address translation byte shift register when the SCLIN N2 to the bus with lower supply. If the voltage difference is low. The translation byte transitions occur approximately is less than 1V, this current is limited to less than 10μA. 100ns after the falling edge of SCLIN. If the SDAIN tran- This allows the input and output buses to be connected sitions sent by the master do not coincide exactly with to nominally identical supplies that may have up ±10% the LTC4316 address translation bit transitions, an extra tolerance, and the LTC4316 V transition on SDAOUT may appear (Figure 7). These extra CC pin can be connected to either supply. SDA transitions are like glitches similar to those occurring during normal Acknowledge bit transitions and do not pose
Extra START and STOP Bits
problems in the system because devices on the bus latch SDA data only when SCL is high. During normal operation, an I2C master should not issue a START or STOP bit within a data byte. I2C slave behavior
Level Translation and Supply Voltage Matching
when such a command is received can be unpredictable. The LTC4316 will recover automatically when an unex- The LTC4316 can operate with different supply voltages pected START or STOP is received during the address byte; on the input and output bus, and it will level shift the however, depending on the state of the translating bits, voltages on the SCLIN, SDAIN, SCLOUT, and SDAOUT 4316fa 10 For more information www.linear.com/LTC4316
