Datasheet LTC4318 (Analog Devices) - 10

LTC4318
operaTion Table 2. Setting the Resistive Divider at XORL
which gives 0110 0010b or 0x62. If the configuration
LOWER
voltages at XORL and XORH pins are the same, they can
4-BIT OF
be tied together and connected to a single resistive divider.
TRANSLATION BYTE
Alternatively, three resistors can be used to configure
RECOMMENDED RECOMMENDED a3 a2 a1 a0 V
the XORL and XORH pins (Figure 6). Use the following
XORL/VCC RLT [kΩ] RLB [kΩ]
0 0 0 0 ≤ 0.03125 Open Short procedure to calculate the value of the three resistors: 0 0 0 1 0.09375 ±0.015 976 102 0 0 1 0 0.15625 ±0.015 976 182 VCC 0 0 1 1 0.21875 ±0.015 1000 280 RA1 VCC 0 1 0 0 0.28125 ±0.015 1000 392 XORL 0 1 0 1 0.34375 ±0.015 1000 523 LTC4318 RA2 0 1 1 0 0.40625 ±0.015 1000 681 XORH 0 1 1 1 0.46875 ±0.015 1000 887 RA3 1 0 0 0 0.53125 ±0.015 887 1000 4318 F06 1 0 0 1 0.59375 ±0.015 681 1000 1 0 1 0 0.65625 ±0.015 523 1000
Figure 6. Address Translation Byte
1 0 1 1 0.71875 ±0.015 392 1000
Configuration Using Three Resistors
1 1 0 0 0.78125 ±0.015 280 1000 1 1 0 1 0.84375 ±0.015 182 976 First choose a total resistance value RTOTAL 1 1 1 0 0.90625 ±0.015 102 976 1 1 1 1 ≥ 0.96875 Short Open RA3 = RTOTAL • (VXORH/VCC) RA2 = (RTOTAL • VXORL/VCC) – RA3
Table 3. Setting the Resistive Divider at XORH
RA1 = RTOTAL – RA3 – RA2
UPPER 3-BIT OF
Use 1% tolerance resistors for RA1, RA2 and RA3.
TRANSLATION BYTE
Once the XORL and XORH pins are read, the LTC4318
RECOMMENDED RECOMMENDED a6 a5 a4 V
turns on switches N1 and N2, connecting the input and
XORH/VCC RHT {kΩ] RHB [kΩ}
0 0 0 ≤ 0.03125 Open Short output, and the READY pin goes high to indicate that the 0 0 1 0.09375 ±0.015 976 102 LTC4318 is ready to start address translation. 0 1 0 0.15625 ±0.015 976 182 The address translation byte can be changed during 0 1 1 0.21875 ±0.015 1000 280 operation by changing the XORH and XORL voltages and 1 0 0 0.28125 ±0.015 1000 392 toggling the ENABLE pin (high-low-high). This triggers 1 0 1 0.34375 ±0.015 1000 523 the LTC4318 to re-read the XORL and XORH voltages. 1 1 0 0.40625 ±0.015 1000 681 1 1 1 0.46875 ±0.015 1000 887
Enable/UVLO
If the ENABLE pin is driven below 1.4V or if VCC is be- For example, if RLT = 976k, RLB = 102k, RHT = 1000k, and low the UVLO threshold, the LTC4318 shuts down. The RHB = 280k, the lower 4 translation bits are 0001b and internal shift register storing the address translation byte the upper 3 bits are 011b. The 8-bit hexadecimal address is cleared, address translation is disabled, switches N1, translation byte is obtained by adding a 0 as the LSB, N2 and N3 are off, the READY pin is pulled low and the quiescent current drops to 350µA. 4318fa 10 For more information www.linear.com/LTC4318