Datasheet ADXL180 (Analog Devices) - 6

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ADXL180 Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
REGULATOR VOLTAGE MONITOR Regulator Operating Voltage VDD 4.20 V Power-Up Reset Voltage VPUR 3.77 4.0 4.23 V See Figure 33 Overvoltage Level VOV 4.7 4.95 5.3 V See Figure 33 Reset Hysteresis Voltage VHYST 0.12 V COMMUNICATIONS INTERFACE Quiescent (Idle) Current ILDLE 5 6 7.7 mA Modulation Current IMOD 23 25 30 mA Signal Current ISIG 28 31 37.7 mA ISIG = IIDLE + IMOD Autodelay Detect Current IDET 18 22 26 mA Total including IIDLE Data Bit Period2 tB 8 μs tB = 8 × tCLK Data Bit Duty Cycle DDC 45 50 53 % DDC = tA/tB, see Figure 7 Data Bit Rise/Fall See Figure 7 Fall Time tR 400 1000 ns Rise Time tF 350 1000 ns Encoding Manchester See Figure 8 ADC Conversion Time2 tADC 35 μs See Figure 12 Error Checking (Selectable) Number of CRC Bits 3 x³ + x¹+ x0 Number of Parity Bits 1 Even Synchronization Pulse Detect No Detect Limit VSPND 3.0 V Detect Threshold VSPT 3.5 V VBP − VBN + VSPT ≤ 14.5 V; see Figure 14 Threshold Hysteresis 0.1 V Synchronization Pulse Detect tSPD 8 tCLK See Figure 14 Time Synchronization Pulse tSPP 40 tCLK See Figure 14 Discharge (Pull-Down) Time Synchronization Mode tSTD 63 tCLK See Figure 14 Transmission Delay Configuration Mode Receive All @ 25°C only; VBP − VBN + VCT ≤ 12.25 V Communications Interface Detect Threshold VCT 5.25 V See Figure 35 Threshold Hysteresis 0.1 V Interbit Time tIB 250 tCLK See Figure 35 Data 0 Pulse Width tPG0 40 55 tCLK See Figure 35 Data 1 Pulse Width tPG1 80 tCLK See Figure 35 Configuration Mode tTM1 24 μs See Figure 35 Response Time Configuration Mode Write tTM2 50 μs See Figure 35 Delay Time VBP During Fuse VBPF 7.5 V Compliant up to the maximum operating Programming voltage VBP Current During Fuse IFP 15 mA Maximum drawn by the part Programming Rev. A | Page 5 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION OVERVIEW ACCELERATION SENSOR SIGNAL PROCESSING DIGITAL COMMUNICATIONS STATE MACHINE 2-WIRE CURRENT MODULATED INTERFACE SYNCHRONOUS OPERATION AND DUAL DEVICE BUS PROGRAMMED MEMORY AND CONFIGURABILITY Factory-Programmed Serial Number and Manufacturer Information User-Programmable Data Register User-Programmed Configuration Physical Layer (ISO Layer 1) Data Link Layer (ISO Layer 2) Application Layer (ISO Layer 7) PHYSICAL INTERFACE APPLICATION CIRCUIT CURRENT MODULATION MANCHESTER DATA ENCODING OPERATION AT LOW VBP OR LOW VDD OPERATION AT HIGH VDD COMMUNICATIONS TIMING AND BUS TOPOLOGIES DATA TRANSMISSION ASYNCHRONOUS COMMUNICATION Asynchronous Single Device Point-to-Point Topology SYNCHRONOUS COMMUNICATION Configuring the ADXL180 for Synchronous Operation Synchronization Pulse Detection Bus Discharge Enable Synchronous Single Device Point-to-Point Topology SYNCHRONOUS COMMUNICATION MODE—DUAL DEVICE Configuring Synchronous Operation Delay Selection Fixed Delay Mode Autodelay Mode Dual Device Synchronous Parallel Topology Dual Device Synchronous Series Topology DATA FRAME DEFINITION DATA FRAME TRANSMISSION FORMAT DATA FRAME CONFIGURATION OPTIONS ACCELERATION DATA CODING STATE VECTOR CODING STATE VECTOR DESCRIPTIONS TRANSMISSION ERROR DETECTION OPTIONS CRC Encoding Parity Encoding APPLICATION LAYER: COMMUNICATION PROTOCOL STATE MACHINE ADXL180 STATE MACHINE PHASE 1: POWER-ON-RESET INITIALIZATION PHASE 2: DEVICE DATA TRANSMISSION Overview Influence of MD on Data Range Device Data Mapping in Phase 2 PHASE 2: MODE DESCRIPTION Mode 0 Asynchronous Mode Synchronous Mode Mode 1 Mode 2 Device Data User Bits and User Register (UREG) 10-Bit Data and Mode 2 Mode 3 Device Data User Register (UREG) Use with State Vector Enabled Illegal Configuration: Mode 3 and 8-Bit Data PHASE 3: SELF-TEST DIAGNOSTIC Concept of Self-Test Internal and External Self-Test Option External Self-Test Internal Self-Test Influence of MD Selections On Transmitted Self-Test Data PHASE 4: AUTO-ZERO INITIALIZATION Fast Auto-Zero Mode Error Reporting PHASE 5: NORMAL OPERATION Slow Auto-Zero Error Reporting SIGNAL RANGE AND FILTERING TRANSFER FUNCTION OVERVIEW RANGE THREE-POLE BESSEL FILTER AUTO-ZERO OPERATION Offset Drift Monitoring ERROR DETECTION OVERVIEW PARITY ERROR DUE TO COMMUNICATIONS PROTOCOL CONFIGURATION BIT ERROR SELF-TEST ERROR OFFSET ERROR/OFFSET DRIFT MONITORING VOLTAGE REGULATOR MONITOR RESET OPERATION TEST AND DIAGNOSTIC TOOLS VSCI SIGNAL CHAIN INPUT TEST PIN VSCO ANALOG SIGNAL CHAIN OUTPUT TEST PIN CONFIGURATION SPECIFICATION OVERVIEW CONFIGURATION MODE TRANSMIT COMMUNICATIONS PROTOCOL CONFIGURATION MODE COMMAND (RECEIVE) COMMUNICATIONS PROTOCOL CONFIGURATION MODE COMMUNICATIONS HANDSHAKING CONFIGURATION AND USER DATA REGISTERS CONFIGURATION MODE EXIT SERIAL NUMBER AND MANUFACTURER IDENTIFICATION DATA REGISTERS PROGRAMMING THE CONFIGURATION AND USER DATA REGISTERS OTP PROGRAMMING CONDITIONS AND CONSIDERATIONS CONFIGURATION/USER REGISTER OTP PARITY CONFIGURATION MODE ERROR REPORTING CONFIGURATION REGISTER REFERENCE UD[7:0] USER DATA BITS UD8 CONFIGURATION BIT BDE SCOE FDLY ADME STI FC[1:0] RG[2:0] MD[1:0] SYEN AZE ERC DAT SVD CUPAR AND CUPRG AXIS OF SENSITIVITY BRANDING OUTLINE DIMENSIONS ORDERING GUIDE