Datasheet ADXL180 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Configurable, High-g, iMEMS® Accelerometer |
| Pages / Page | 61 / 10 — ADXL180. TERMINOLOGY Full-Scale Range (FSR). Idle Current. Modulation … |
| Revision | B |
| File Format / Size | PDF / 630 Kb |
| Document Language | English |
ADXL180. TERMINOLOGY Full-Scale Range (FSR). Idle Current. Modulation Current. Noise. Phase. Mode. Sensitivity. CRC. Scale Factor. Offset
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ADXL180 TERMINOLOGY Full-Scale Range (FSR) Idle Current
Idle current is the current of the device when at rest, waiting for The full-scale range of a device, also referred to as the dynamic a synchronization pulse, or in between current modulation. range, is the maximum and minimum g level that reports on the output following the internal filtering. As a reference, there is
Modulation Current
usually a trade-off in increased sensitivity and resolution for Modulation current is the amount of current that the ADXL180 decreased full-scale range, and vice versa. device pulls from the bus when communicating. For more information, see Figure 7.
Noise
Device noise is the noise content between 10 Hz and 400 Hz, as
Phase
noted in the Specifications Table 1. Device noise can be measured A phase is a stage in the ADXL180 state machine. For more by performing an FFT on the digital output and measuring the information, see Figure 22. noise content between the specified frequency limits.
Mode Sensitivity
Mode refers to the selection of the Phase 2 method of device The sensitivity of a device is the amount of output change per data communication. The ADXL180 is configurable into four input change. In this device, it is most usually referred to in unique operating modes. units of LSB/g.
CRC Scale Factor
A cyclic redundancy check (CRC) is calculated from a set of data and then transmitted alongside that data. If the calculation The scale factor is the amount of input change per output change. technique is defined and known to the receiving device, the In this device, it is most usually referred to in units of g/LSB. receiver can then check whether the CRC bits match the data. If
Offset
they do not match, a transmission error has occurred. Offset is the low frequency component of the output signal that
Parity
is not due to changes in input acceleration. Slow moving effects, Parity is defined by the count of 1s in a binary string of data. such as temperature changes and self-heating during start up, If this count is even, then the data is determined to have even may affect offset, but the time scale for these effects is beyond parity. Often a bit is used, such as the CUPAR, in a configuration that of a typical shock or crash event. register that is defined in such a way as to establish a particular
Auto-Zero
parity in the register to detect single bit changes during the life Auto-zero is an offset compensation technique intended to of the device. This is possible because a single bit change changes reduce the long term offset drift effects of temperature and parity and a monitor circuit can detect this. Similarly, a parity aging. This technique is designed to limit interaction with true bit can be added in a data transmission to detect single bit errors acceleration signals. For more information, see Figure 32. if the parity of communication is preestablished for the transmit
Rise/Fall Times
and receive systems. The device rise time is defined as the amount of time necessary for the Manchester encoded signal (IMOD) to transition from 10% to 90% of its final value (ISIG). Device fall time is the amount of time required for the I MOD signal to fall from 90% of ISIG to within 10% of IIDLE. Rev. A | Page 9 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION OVERVIEW ACCELERATION SENSOR SIGNAL PROCESSING DIGITAL COMMUNICATIONS STATE MACHINE 2-WIRE CURRENT MODULATED INTERFACE SYNCHRONOUS OPERATION AND DUAL DEVICE BUS PROGRAMMED MEMORY AND CONFIGURABILITY Factory-Programmed Serial Number and Manufacturer Information User-Programmable Data Register User-Programmed Configuration Physical Layer (ISO Layer 1) Data Link Layer (ISO Layer 2) Application Layer (ISO Layer 7) PHYSICAL INTERFACE APPLICATION CIRCUIT CURRENT MODULATION MANCHESTER DATA ENCODING OPERATION AT LOW VBP OR LOW VDD OPERATION AT HIGH VDD COMMUNICATIONS TIMING AND BUS TOPOLOGIES DATA TRANSMISSION ASYNCHRONOUS COMMUNICATION Asynchronous Single Device Point-to-Point Topology SYNCHRONOUS COMMUNICATION Configuring the ADXL180 for Synchronous Operation Synchronization Pulse Detection Bus Discharge Enable Synchronous Single Device Point-to-Point Topology SYNCHRONOUS COMMUNICATION MODE—DUAL DEVICE Configuring Synchronous Operation Delay Selection Fixed Delay Mode Autodelay Mode Dual Device Synchronous Parallel Topology Dual Device Synchronous Series Topology DATA FRAME DEFINITION DATA FRAME TRANSMISSION FORMAT DATA FRAME CONFIGURATION OPTIONS ACCELERATION DATA CODING STATE VECTOR CODING STATE VECTOR DESCRIPTIONS TRANSMISSION ERROR DETECTION OPTIONS CRC Encoding Parity Encoding APPLICATION LAYER: COMMUNICATION PROTOCOL STATE MACHINE ADXL180 STATE MACHINE PHASE 1: POWER-ON-RESET INITIALIZATION PHASE 2: DEVICE DATA TRANSMISSION Overview Influence of MD on Data Range Device Data Mapping in Phase 2 PHASE 2: MODE DESCRIPTION Mode 0 Asynchronous Mode Synchronous Mode Mode 1 Mode 2 Device Data User Bits and User Register (UREG) 10-Bit Data and Mode 2 Mode 3 Device Data User Register (UREG) Use with State Vector Enabled Illegal Configuration: Mode 3 and 8-Bit Data PHASE 3: SELF-TEST DIAGNOSTIC Concept of Self-Test Internal and External Self-Test Option External Self-Test Internal Self-Test Influence of MD Selections On Transmitted Self-Test Data PHASE 4: AUTO-ZERO INITIALIZATION Fast Auto-Zero Mode Error Reporting PHASE 5: NORMAL OPERATION Slow Auto-Zero Error Reporting SIGNAL RANGE AND FILTERING TRANSFER FUNCTION OVERVIEW RANGE THREE-POLE BESSEL FILTER AUTO-ZERO OPERATION Offset Drift Monitoring ERROR DETECTION OVERVIEW PARITY ERROR DUE TO COMMUNICATIONS PROTOCOL CONFIGURATION BIT ERROR SELF-TEST ERROR OFFSET ERROR/OFFSET DRIFT MONITORING VOLTAGE REGULATOR MONITOR RESET OPERATION TEST AND DIAGNOSTIC TOOLS VSCI SIGNAL CHAIN INPUT TEST PIN VSCO ANALOG SIGNAL CHAIN OUTPUT TEST PIN CONFIGURATION SPECIFICATION OVERVIEW CONFIGURATION MODE TRANSMIT COMMUNICATIONS PROTOCOL CONFIGURATION MODE COMMAND (RECEIVE) COMMUNICATIONS PROTOCOL CONFIGURATION MODE COMMUNICATIONS HANDSHAKING CONFIGURATION AND USER DATA REGISTERS CONFIGURATION MODE EXIT SERIAL NUMBER AND MANUFACTURER IDENTIFICATION DATA REGISTERS PROGRAMMING THE CONFIGURATION AND USER DATA REGISTERS OTP PROGRAMMING CONDITIONS AND CONSIDERATIONS CONFIGURATION/USER REGISTER OTP PARITY CONFIGURATION MODE ERROR REPORTING CONFIGURATION REGISTER REFERENCE UD[7:0] USER DATA BITS UD8 CONFIGURATION BIT BDE SCOE FDLY ADME STI FC[1:0] RG[2:0] MD[1:0] SYEN AZE ERC DAT SVD CUPAR AND CUPRG AXIS OF SENSITIVITY BRANDING OUTLINE DIMENSIONS ORDERING GUIDE
ADXL180 TERMINOLOGY Full-Scale Range (FSR) Idle Current
Idle current is the current of the device when at rest, waiting for The full-scale range of a device, also referred to as the dynamic a synchronization pulse, or in between current modulation. range, is the maximum and minimum g level that reports on the output following the internal filtering. As a reference, there is
Modulation Current
usually a trade-off in increased sensitivity and resolution for Modulation current is the amount of current that the ADXL180 decreased full-scale range, and vice versa. device pulls from the bus when communicating. For more information, see Figure 7.
Noise
Device noise is the noise content between 10 Hz and 400 Hz, as
Phase
noted in the Specifications Table 1. Device noise can be measured A phase is a stage in the ADXL180 state machine. For more by performing an FFT on the digital output and measuring the information, see Figure 22. noise content between the specified frequency limits.
Mode Sensitivity
Mode refers to the selection of the Phase 2 method of device The sensitivity of a device is the amount of output change per data communication. The ADXL180 is configurable into four input change. In this device, it is most usually referred to in unique operating modes. units of LSB/g.
CRC Scale Factor
A cyclic redundancy check (CRC) is calculated from a set of data and then transmitted alongside that data. If the calculation The scale factor is the amount of input change per output change. technique is defined and known to the receiving device, the In this device, it is most usually referred to in units of g/LSB. receiver can then check whether the CRC bits match the data. If
Offset
they do not match, a transmission error has occurred. Offset is the low frequency component of the output signal that
Parity
is not due to changes in input acceleration. Slow moving effects, Parity is defined by the count of 1s in a binary string of data. such as temperature changes and self-heating during start up, If this count is even, then the data is determined to have even may affect offset, but the time scale for these effects is beyond parity. Often a bit is used, such as the CUPAR, in a configuration that of a typical shock or crash event. register that is defined in such a way as to establish a particular
Auto-Zero
parity in the register to detect single bit changes during the life Auto-zero is an offset compensation technique intended to of the device. This is possible because a single bit change changes reduce the long term offset drift effects of temperature and parity and a monitor circuit can detect this. Similarly, a parity aging. This technique is designed to limit interaction with true bit can be added in a data transmission to detect single bit errors acceleration signals. For more information, see Figure 32. if the parity of communication is preestablished for the transmit
Rise/Fall Times
and receive systems. The device rise time is defined as the amount of time necessary for the Manchester encoded signal (IMOD) to transition from 10% to 90% of its final value (ISIG). Device fall time is the amount of time required for the I MOD signal to fall from 90% of ISIG to within 10% of IIDLE. Rev. A | Page 9 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION OVERVIEW ACCELERATION SENSOR SIGNAL PROCESSING DIGITAL COMMUNICATIONS STATE MACHINE 2-WIRE CURRENT MODULATED INTERFACE SYNCHRONOUS OPERATION AND DUAL DEVICE BUS PROGRAMMED MEMORY AND CONFIGURABILITY Factory-Programmed Serial Number and Manufacturer Information User-Programmable Data Register User-Programmed Configuration Physical Layer (ISO Layer 1) Data Link Layer (ISO Layer 2) Application Layer (ISO Layer 7) PHYSICAL INTERFACE APPLICATION CIRCUIT CURRENT MODULATION MANCHESTER DATA ENCODING OPERATION AT LOW VBP OR LOW VDD OPERATION AT HIGH VDD COMMUNICATIONS TIMING AND BUS TOPOLOGIES DATA TRANSMISSION ASYNCHRONOUS COMMUNICATION Asynchronous Single Device Point-to-Point Topology SYNCHRONOUS COMMUNICATION Configuring the ADXL180 for Synchronous Operation Synchronization Pulse Detection Bus Discharge Enable Synchronous Single Device Point-to-Point Topology SYNCHRONOUS COMMUNICATION MODE—DUAL DEVICE Configuring Synchronous Operation Delay Selection Fixed Delay Mode Autodelay Mode Dual Device Synchronous Parallel Topology Dual Device Synchronous Series Topology DATA FRAME DEFINITION DATA FRAME TRANSMISSION FORMAT DATA FRAME CONFIGURATION OPTIONS ACCELERATION DATA CODING STATE VECTOR CODING STATE VECTOR DESCRIPTIONS TRANSMISSION ERROR DETECTION OPTIONS CRC Encoding Parity Encoding APPLICATION LAYER: COMMUNICATION PROTOCOL STATE MACHINE ADXL180 STATE MACHINE PHASE 1: POWER-ON-RESET INITIALIZATION PHASE 2: DEVICE DATA TRANSMISSION Overview Influence of MD on Data Range Device Data Mapping in Phase 2 PHASE 2: MODE DESCRIPTION Mode 0 Asynchronous Mode Synchronous Mode Mode 1 Mode 2 Device Data User Bits and User Register (UREG) 10-Bit Data and Mode 2 Mode 3 Device Data User Register (UREG) Use with State Vector Enabled Illegal Configuration: Mode 3 and 8-Bit Data PHASE 3: SELF-TEST DIAGNOSTIC Concept of Self-Test Internal and External Self-Test Option External Self-Test Internal Self-Test Influence of MD Selections On Transmitted Self-Test Data PHASE 4: AUTO-ZERO INITIALIZATION Fast Auto-Zero Mode Error Reporting PHASE 5: NORMAL OPERATION Slow Auto-Zero Error Reporting SIGNAL RANGE AND FILTERING TRANSFER FUNCTION OVERVIEW RANGE THREE-POLE BESSEL FILTER AUTO-ZERO OPERATION Offset Drift Monitoring ERROR DETECTION OVERVIEW PARITY ERROR DUE TO COMMUNICATIONS PROTOCOL CONFIGURATION BIT ERROR SELF-TEST ERROR OFFSET ERROR/OFFSET DRIFT MONITORING VOLTAGE REGULATOR MONITOR RESET OPERATION TEST AND DIAGNOSTIC TOOLS VSCI SIGNAL CHAIN INPUT TEST PIN VSCO ANALOG SIGNAL CHAIN OUTPUT TEST PIN CONFIGURATION SPECIFICATION OVERVIEW CONFIGURATION MODE TRANSMIT COMMUNICATIONS PROTOCOL CONFIGURATION MODE COMMAND (RECEIVE) COMMUNICATIONS PROTOCOL CONFIGURATION MODE COMMUNICATIONS HANDSHAKING CONFIGURATION AND USER DATA REGISTERS CONFIGURATION MODE EXIT SERIAL NUMBER AND MANUFACTURER IDENTIFICATION DATA REGISTERS PROGRAMMING THE CONFIGURATION AND USER DATA REGISTERS OTP PROGRAMMING CONDITIONS AND CONSIDERATIONS CONFIGURATION/USER REGISTER OTP PARITY CONFIGURATION MODE ERROR REPORTING CONFIGURATION REGISTER REFERENCE UD[7:0] USER DATA BITS UD8 CONFIGURATION BIT BDE SCOE FDLY ADME STI FC[1:0] RG[2:0] MD[1:0] SYEN AZE ERC DAT SVD CUPAR AND CUPRG AXIS OF SENSITIVITY BRANDING OUTLINE DIMENSIONS ORDERING GUIDE
