Datasheet AD7740 (Analog Devices) - 3

AD7740 SPECIFICATIONS (VDD = 3.0 V to 3.6 V, 4.75 V to 5.25 V, GND = 0 V, REFIN = 2.5 V; CLKIN = 1 MHz; All specifications TMIN to TMAX unless otherwise noted.) K, Y Versions1 Parameter2 Min Typ Max Unit Test Conditions/Comments
DC PERFORMANCE Integral Nonlinearity CLKIN = 32 kHz3 ±0.012 % of Span4 Unbuffered Mode, External Clock at CLKIN CLKIN = 1 MHz ±0.012 % of Span Unbuffered Mode, Crystal at CLKIN CLKIN = 32 kHz3 ±0.018 % of Span Buffered Mode, External Clock at CLKIN CLKIN = 1 MHz ±0.018 % of Span Buffered Mode, Crystal at CLKIN Offset Error ±7 ±35 mV Unbuffered Mode, VIN = 0 V ±7 ±35 mV Buffered Mode, VIN = 0.1 V Gain Error ±0.1 ±0.7 % of Span Offset Error Drift3 ±20 µV/°C Gain Error Drift3 ±4 ppm of Span/°C Power Supply Rejection Ratio3 –55 dB ∆VDD = ±5% (5 V) –65 dB ∆VDD = ±10% (3.3 V) ANALOG INPUT, VIN Nominal Input Span 0 – VREF V ±150 mV Overrange Available 0.1 VDD – 0.2 V Buffered Mode Input Current 8 10 µA Unbuffered Mode, VIN = 5.4 V, REFIN = 5.25 V 5 100 nA Buffered Mode, VIN = 0.1 V, REFIN = 2.5 V REFERENCE VOLTAGE REFIN5 Nominal Input Voltage 2.5 VDD V REFOUT Output Voltage 2.3 2.5 2.7 V Output Impedance3 1 kΩ See Pin Function Description Reference Drift3 ±50 ppm/°C Line Rejection3 –75 dB ∆VDD = ±5% (5 V) Line Rejection3 –60 dB ∆VDD = ±10% (3.3 V) Reference Noise (0.1 Hz to 10 Hz)3 100 µV p–p FOUT OUTPUT Nominal Frequency Span 0.1 fCLKIN to 0.9 fCLKIN Hz VIN = 0 V to VREF. See Figure 2 LOGIC INPUTS (CLKIN, BUF)3 CLKIN Input Frequency 32 1000 kHz For Specified Performance Input High Voltage, VIH 3.5 V VDD = 5 V ± 5% Input High Voltage, VIH 2.5 V VDD = 3.3 V ± 10% Input Low Voltage, VIL 0.8 V VDD = 5 V ± 5% Input Low Voltage, VIL 0.4 V VDD = 3.3 V ± 10% Input Current ±2 µA VIN = 0 V to VDD Pin Capacitance 3 10 pF BUF Input High Voltage, VIH 2.4 V VDD = 5 V ± 5% Input High Voltage, VIH 2.1 V VDD = 3.3 V ± 10% Input Low Voltage, VIL 0.8 V VDD = 5 V ± 5% Input Low Voltage, VIL 0.4 V VDD = 3.3 V ± 10% Input Current ±100 nA Pin Capacitance 3 10 pF LOGIC OUTPUTS (FOUT, CLKOUT)3 Output High Voltage, VOH 4.0 V Output Sourcing 200 µA6. VDD = 5 V ± 5% Output High Voltage, VOH 2.1 V Output Sourcing 200 µA6. VDD = 3.3 V ± 10% Output Low Voltage, VOL 0.1 0.4 V Output Sinking 1.6 mA6 POWER REQUIREMENTS V 7 DD 3.0 5.25 V IDD (Normal Mode)8 0.9 1.25 mA VIH = VDD, VIL= GND. Unbuffered Mode IDD (Normal Mode)8 1.1 1.5 mA VIH = VDD, VIL= GND. Buffered Mode IDD (Power-Down) 30 100 µA Power-Up Time3 30 µs Exiting Power-Down (Ext. Clock at CLKIN) NOTES 1Temperature range: K Version, 0°C to +85°C; Y Version, –40°C to +105°C; typical specifications are at 25°C. 2See Terminology. 3Guaranteed by design and characterization, not production tested. 4Span = Max output frequency–Min output frequency. 5Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400 µA in order to overdrive the internal reference. 6These logic levels apply to CLKOUT only when it is loaded with one CMOS load. 7Operation at VDD = 2.7 V is also possible with degraded specifications. 8Outputs unloaded. IDD increases by CL × VOUT × fFOUT when FOUT is loaded. If using a crystal/resonator as the clock source, IDD will vary depending on the crystal/resonator type (see Clock Generation section). Specifications subject to change without notice. –2– REV. C